公开(公告)号：US11703478B2

公开(公告)日：2023-07-18

申请号：US16957614

申请日：2019-07-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaoxin Song ,  Feng Zhang ,  Wenqu Liu ,  Zhijun Lv ,  Liwen Dong ,  Zhao Cui ,  Detian Meng ,  Libo Wang ,  Qi Yao

IPC: G01N29/02

CPC classification number: G01N29/022 ,  G01N2291/0228

Abstract: A micro total analysis system, operating method and manufacturing method thereof are provided. The micro total analysis system includes at least one micro total analysis unit each including: microfluidic device including first electrode and dielectric layer connected to each other, where the dielectric layer drives to-be-measured droplet to move based on voltage of the first electrode; and acoustic wave detection device including second electrode connected to the dielectric layer, where the dielectric layer is also used as transducer of the acoustic wave detection device, and configured to generate acoustic wave toward the droplet based on voltage of the second electrode, and generate a detection result corresponding to the droplet based on received acoustic wave. The micro total analysis system, the operating method and the manufacturing method thereof enables the microfluidic device and the acoustic wave detection device to be integrated in the same chip.

公开(公告)号：US11678530B2

公开(公告)日：2023-06-13

申请号：US17359675

申请日：2021-06-28

Applicant: BOE Technology Group Co., Ltd.

Inventor： Wenqu Liu ,  Qi Yao ,  Detian Meng ,  Feng Zhang ,  Zhao Cui ,  Liwen Dong ,  Xiaoxin Song ,  Dongfei Hou ,  Libo Wang ,  Zhijun Lv

IPC: H01L29/32 ,  H10K59/126 ,  H01L29/786 ,  H10K71/00

CPC classification number: H10K59/126 ,  H01L29/7869 ,  H01L29/78672 ,  H10K71/00

Abstract: Provided are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a substrate, an active structure layer disposed on the substrate, a first source-drain structure layer disposed on a side of the active structure layer away from the substrate, and a second source-drain structure layer disposed on a side of the first source-drain structure layer away from the substrate. The active structure layer includes a first active layer and a second active layer. The first source-drain structure layer includes a first active via and a first source-drain electrode, and the first source-drain electrode is connected to the first active layer through the first active via; and the second source-drain structure layer includes a second active via and a second source-drain electrode, and the second source-drain electrode is connected to the second active layer through the second active via.

公开(公告)号：US11442583B2

公开(公告)日：2022-09-13

申请号：US16966394

申请日：2020-01-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wenqu Liu ,  Xiufeng Li ,  Qi Yao ,  Feng Zhang ,  Liwen Dong ,  Zhao Cui ,  Chuanxiang Xu ,  Detian Meng ,  Xiaoxin Song ,  Libo Wang ,  Yang Yue ,  Dongfei Hou ,  Zhijun Lv

IPC: G06F3/043 ,  H01L41/04 ,  H01L41/047 ,  H01L41/083 ,  H01L41/113 ,  H01L41/27 ,  G06F3/044 ,  G06F3/041 ,  G06V40/13 ,  G06V40/12

Abstract: A fingerprint identification module, a manufacturing method thereof and an electronic device are disclosed. In the fingerprint identification module, an auxiliary structure is at least partially located on a functional substrate, and a plurality of first driving electrodes are on a side, away from the functional substrate, of the piezoelectric material and the auxiliary structure; each first driving electrode extends along a first direction and exceeds a first edge of the piezoelectric material layer in the first direction; the plurality of first driving electrodes are arranged at intervals along a second direction; the auxiliary structure is at least in contact with the first edge; the auxiliary structure includes a slope portion; and a thickness of the slope portion in a direction perpendicular to the functional substrate gradually decreases in a direction from the first edge to a position away from a center of the piezoelectric material layer.

公开(公告)号：US11387308B2

公开(公告)日：2022-07-12

申请号：US16071681

申请日：2017-12-11

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Feng Zhang ,  Zhijun Lv ,  Wenqu Liu ,  Liwen Dong ,  Shizheng Zhang ,  Ning Dang ,  Zhiyong Liu

IPC: H01L27/32 ,  H01L29/786

Abstract: The present application discloses an array substrate having a plurality of first thin film transistors and a plurality of second thin film transistors. Each of the plurality of first thin film transistors includes a silicon active layer. The array substrate includes a base substrate; a silicon layer having a plurality of silicon active layers respectively for the plurality of first thin film transistors; and a UV absorption layer on a side of the silicon layer distal to the base substrate, and including a plurality of UV absorption blocks. Each of the plurality of UV absorption blocks is on a side of the one of the plurality of silicon active layers distal to the base substrate, and is insulated from the one of the plurality of silicon active layers.

公开(公告)号：US11327215B2

公开(公告)日：2022-05-10

申请号：US16649651

申请日：2019-03-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Shuilang Dong ,  Xiandong Meng ,  Wenqu Liu ,  Jifeng Tan ,  Wei Tan

IPC: F21V8/00 ,  G02B1/14 ,  C23F1/02 ,  G03F7/00

Abstract: The present disclosure provides a collimating backlight module, a preparation method thereof and a display device. The method for preparing the collimating backlight module includes: providing a light guide plate; forming a protective layer on a light emitting side of the light guide plate, where the protective layer simultaneously covers a light emitting area and a non-light emitting area of the light emitting side, a hollow area is formed on the protective layer, to expose the light emitting area of the light guide plate; and forming a light taking grating on the light emitting area of the light guide plate.

公开(公告)号：US11296165B2

公开(公告)日：2022-04-05

申请号：US16755643

申请日：2019-05-20

Applicant: BOE Technology Group Co., Ltd.

Inventor： Feng Zhang ,  Zhijun Lv ,  Wenqu Liu ,  Liwen Dong ,  Xiaoxin Song ,  Zhao Cui ,  Detian Meng ,  Libo Wang ,  Chuanxiang Xu

IPC: H01L27/32 ,  H01L51/00 ,  H01L51/56

Abstract: An array substrate includes a flexible base substrate; a buffer layer on the flexible base substrate and continuously extending from a display area into a peripheral area, including a first portion substantially extending throughout the display area and a second portion in the peripheral area, the first portion and the second portion being parts of an integral layer, an organic insulating layer substantially extending throughout but limited in the display area and on a side of the buffer layer away from the flexible base substrate; an inorganic insulating layer limited in the peripheral area and on a side of the buffer layer away from the flexible base substrate; a planarization layer on a side of the organic insulating layer away from the buffer layer, and a plurality of light emitting elements on a side of the planarization layer away from the organic insulating layer.

公开(公告)号：US10985225B2

公开(公告)日：2021-04-20

申请号：US15989014

申请日：2018-05-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Feng Zhang ,  Wenqu Liu ,  Zhijun Lv ,  Liwen Dong ,  Shizheng Zhang ,  Ning Dang

IPC: H01L27/32 ,  H01L51/56 ,  H01L51/52 ,  H01L51/00 ,  H01L51/50

Abstract: The present disclosure provides a method for manufacturing an OLED display substrate, including a step of forming a pattern of a pixel definition layer on a substrate through a patterning process. A bottom wall of the pixel definition layer is formed on the substrate, a top wall of the pixel definition layer is arranged parallel to the bottom wall, and a side wall of the pixel definition layer is angled relative to the top wall at an acute angle.

公开(公告)号：US10546905B2

公开(公告)日：2020-01-28

申请号：US16023400

申请日：2018-06-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wenqu Liu ,  Liwen Dong ,  Feng Zhang ,  Zhijun Lv ,  Ning Dang ,  Shizheng Zhang

IPC: H01L27/32 ,  H01L51/00 ,  H01L51/52 ,  H01L51/56

Abstract: The present invention provides a method for manufacturing an array substrate, including; a step of providing a substrate; a step of making an electrode layer on the substrate; and a step of making a spacer layer and a spacer column on the electrode layer; wherein the spacer column is made by heat-treatment while the spacer layer is being formed, and a method for manufacturing an array substrate. The method for manufacturing an array substrate provided by the present invention can not only shorten the production cycle, lower the production cost, but also avoid the threshold voltage drift of the TFT due to the irradiation of a large area of ultraviolet rays.