公开(公告)号：US07405455B2

公开(公告)日：2008-07-29

申请号：US11126455

申请日：2005-05-10

Applicant: Leonard Forbes ,  Kie Y. Ahn ,  Luan C. Tran

Inventor： Leonard Forbes ,  Kie Y. Ahn ,  Luan C. Tran

IPC: H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/28273 ,  H01L29/4941 ,  H01L29/6656

Abstract: One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first-layered-defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second-layer-defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.

Abstract translation: 本发明的一个方面包括形成半导体结构的方法。 形成图案线以包括第一层和第二层。 第一层包括硅，第二层包括金属。 线具有包括第一层限定部分和第二层限定部分的至少一个侧壁边缘。 沿着至少一个侧壁边缘形成第三层。 第三层包括硅并沿着侧壁边缘的第一层限定部分和侧壁边缘的第二层限定部分。 第三层的硅与第二层的金属反应，沿着侧壁边缘的第二层限定部分形成硅化物。 去除第三层的硅以留下第一层的硅，第二层的金属和硅化物。

公开(公告)号：US07378311B2

公开(公告)日：2008-05-27

申请号：US10929046

申请日：2004-08-27

Applicant: Luan C. Tran

Inventor： Luan C. Tran

IPC: H01L21/8239 ,  H01L21/8242

CPC classification number: H01L27/10873 ,  H01L27/0214 ,  H01L27/10894 ,  Y10S257/906 ,  Y10S438/981

Abstract: The invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.

Abstract translation: 本发明包括形成在半导体衬底上的6F 2 DRAM阵列。 存储器阵列包括第一存储单元。 第一存储单元包括第一存取晶体管和第一数据存储电容器。 第一存取晶体管的第一负载电极经由形成在衬底上的第一存储节点耦合到第一数据存储电容器。 存储器阵列还包括第二存储器单元。 第二存储单元包括第二存取晶体管和第二数据存储电容器。 第二存取晶体管的第一负载电极经由形成在基板上的第二存储节点耦合到第二数据存储电容器。 第一和第二存取晶体管具有具有第一厚度的栅极电介质。 存储器阵列还包括形成在第一和第二存储节点之间并被配置为在它们之间提供电隔离的隔离栅极。 隔离栅极具有第二厚度大于第一厚度的栅极电介质。 隔离栅极电介质可以在衬底的表面上方或下方延伸。

公开(公告)号：US06806123B2

公开(公告)日：2004-10-19

申请号：US10133193

申请日：2002-04-26

Applicant: Mark McQueen ,  Luan C. Tran ,  Chandra Mouli

Inventor： Mark McQueen ,  Luan C. Tran ,  Chandra Mouli

IPC: H01L21332

CPC classification number: H01L27/10873 ,  H01L21/28123 ,  H01L27/105 ,  H01L27/10882 ,  H01L27/10894

Abstract: The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped to at least 1×1017 atoms/cm3 with n-type and p-type dopant. The invention also includes a semiconductor construction in which a doped material is over a segment of a substrate. The doped material has a first type majority dopant therein, and is electrically connected with an electrical ground. A pair of conductively-doped diffusion regions are adjacent the segment, and spaced from one another by at least a portion of the segment. The conductively-doped diffusion regions have a second type majority dopant therein. The invention also encompasses methods of forming semiconductor constructions.

Abstract translation: 本发明包括其中具有结构的DRAM阵列，其包括通过中间绝缘材料与第二材料分离的第一材料。 第一种材料与n型和p型掺杂剂掺杂至至少1×10 17个原子/ cm 3。 本发明还包括半导体结构，其中掺杂材料在衬底的一段上方。 掺杂材料在其中具有第一类型多数掺杂剂，并且与电接地电连接。 一对导电掺杂的扩散区域与该段相邻，并且通过该段的至少一部分彼此间隔开。 导电掺杂扩散区域中具有第二类型多数掺杂剂。 本发明还包括形成半导体结构的方法。

公开(公告)号：US06720638B2

公开(公告)日：2004-04-13

申请号：US10355678

申请日：2003-01-30

Applicant: Luan C. Tran

Inventor： Luan C. Tran

IPC: H01L2900

CPC classification number: H01L21/76224 ,  H01L21/763

Abstract: The invention includes a semiconductor construction. The construction includes a semiconductive material having a surface and an opening extending through the surface. An electrically insulative liner is along a periphery of the opening. A mass comprising one or more of silicon, germanium, metal, metal silicide and dopant is within a bottom portion of the opening, and only partially fills the opening. The mass has a top surface. An electrically insulative material is within the opening and over the top surface of the mass. The top surface of the mass is at least about 200 Angstroms beneath the surface of the semiconductive material. The invention also includes methods of forming semiconductor constructions.

公开(公告)号：US06600190B2

公开(公告)日：2003-07-29

申请号：US09730865

申请日：2000-12-05

Applicant: Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  D. Mark Durcan

Inventor： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  D. Mark Durcan

IPC: H01L27108

CPC classification number: H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

Abstract translation: 描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。 在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。 随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。 在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。

公开(公告)号：US06599800B2

公开(公告)日：2003-07-29

申请号：US09954340

申请日：2001-09-14

Applicant: Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  Mark Durcan

Inventor： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  Mark Durcan

IPC: A01L218242

CPC classification number: H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

Abstract translation: 描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。 在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。 随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。 在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。

公开(公告)号：US06548390B1

公开(公告)日：2003-04-15

申请号：US10153830

申请日：2002-05-21

Applicant: Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

Inventor： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

IPC: H01L2144

CPC classification number: H01L27/10888 ,  H01L21/32051 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

Abstract: Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

公开(公告)号：US06545904B2

公开(公告)日：2003-04-08

申请号：US09810933

申请日：2001-03-16

Applicant: Luan C. Tran

Inventor： Luan C. Tran

IPC: G11C700

CPC classification number: H01L27/10873 ,  H01L27/0214 ,  H01L27/10894 ,  Y10S257/906 ,  Y10S438/981

Abstract: The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.

Abstract translation: 本发明包括形成在半导体衬底上的6F2 DRAM阵列。 存储器阵列包括第一存储单元。 第一存储单元包括第一存取晶体管和第一数据存储电容器。 第一存取晶体管的第一负载电极经由形成在衬底上的第一存储节点耦合到第一数据存储电容器。 存储器阵列还包括第二存储器单元。 第二存储单元包括第二存取晶体管和第二数据存储电容器。 第二存取晶体管的第一负载电极经由形成在基板上的第二存储节点耦合到第二数据存储电容器。 第一和第二存取晶体管具有具有第一厚度的栅极电介质。 存储器阵列还包括形成在第一和第二存储节点之间并被配置为在它们之间提供电隔离的隔离栅极。 隔离栅极具有第二厚度大于第一厚度的栅极电介质。 隔离栅极电介质可以在衬底的表面上方或下方延伸。

公开(公告)号：US06455407B2

公开(公告)日：2002-09-24

申请号：US09765236

申请日：2001-01-16

Applicant: Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

Inventor： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

IPC: H01L214763

CPC classification number: H01L27/10888 ,  H01L21/32051 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

Abstract: Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

Abstract translation: 描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。 在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。 位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。 材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。 随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

公开(公告)号：US06440825B1

公开(公告)日：2002-08-27

申请号：US09616540

申请日：2000-07-14

Applicant: Fernando González ,  D. Mark Durcan ,  Luan C. Tran ,  Robert B. Kerr ,  David F. Cheffings ,  Howard E. Rhodes

Inventor： Fernando González ,  D. Mark Durcan ,  Luan C. Tran ,  Robert B. Kerr ,  David F. Cheffings ,  Howard E. Rhodes

IPC: H01L2170

CPC classification number: H01L27/10852 ,  H01L28/82

Abstract: A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.

Abstract translation: 用于控制来自三维膜的向外扩散量的固态制造技术包括以限定上部和下部的方式提供第一层原位掺杂膜的步骤。 第二层未掺杂的膜设置在第一层的顶部上，以类似地限定上部和下部。 根据预定图案蚀刻第一层和第二层。 掺杂第二层以获得从上部向下部减小的期望的掺杂剂密度。 从第二层的上部扩散掺杂剂导致掺杂剂迁移到第二层的下部。 因此，消除或大大降低了向基板的扩散和由此引起的问题。