知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

52 records (took 0.033 seconds)

    Using multiple functional blocks for training neural networks
    41.
    发明授权
    Using multiple functional blocks for training neural networks 有权

    公开(公告)号：US11880769B2

    公开(公告)日：2024-01-23

    申请号：US16191359

    申请日：2018-11-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sudhanva Gurumurthi

    IPC: G06N3/084 ,  G06N3/04 ,  G06N3/065

    CPC classification number: G06N3/084 ,  G06N3/04 ,  G06N3/065

    Abstract: A system is described that performs training operations for a neural network, the system including an analog circuit element functional block with an array of analog circuit elements, and a controller. The controller monitors error values computed using an output from each of one or more initial iterations of a neural network training operation, the one or more initial iterations being performed using neural network data acquired from the memory. When one or more error values are less than a threshold, the controller uses the neural network data from the memory to configure the analog circuit element functional block to perform remaining iterations of the neural network training operation. The controller then causes the analog circuit element functional block to perform the remaining iterations.

    HOST-LEVEL ERROR DETECTION AND FAULT CORRECTION
    42.
    发明公开
    HOST-LEVEL ERROR DETECTION AND FAULT CORRECTION 审中-公开

    公开(公告)号：US20230409426A1

    公开(公告)日：2023-12-21

    申请号：US17841864

    申请日：2022-06-16

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Sudhanva Gurumurthi ,  Vilas Sridharan

    IPC: G06F11/10 ,  G06F11/07

    CPC classification number: G06F11/1004 ,  G06F11/102 ,  G06F11/1068 ,  G06F11/0772

    Abstract: A processing system includes a processing device coupled to a memory configured to check for and correct faults in requested data. In response to correcting the faults of the requested data, the memory sends the corrected data and unused check bits to the processing device as a plurality of fetch returns. The memory also sends a parity fetch based on the corrected data and one or more operations to the processing device. After receiving the plurality of fetch returns and the unused check bits, the processing device checks each fetch return for faults based on the unused check bits. In response to determining that a fetch return includes a fault, the processing device erases the fetch return and reconstructs the fetch return based on one or more other received fetch returns and the parity fetch.

    Using Sub-Networks Created from Neural Networks for Processing Color Images
    46.
    发明申请
    Using Sub-Networks Created from Neural Networks for Processing Color Images 有权

    公开(公告)号：US20210049446A1

    公开(公告)日：2021-02-18

    申请号：US16538764

    申请日：2019-08-12

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sudhanva Gurumurthi ,  Abhinav Vishnu

    IPC: G06N3/04 ,  G06T7/90 ,  G06N20/20

    Abstract: A system comprising an electronic device that includes a processor is described. During operation, the processor acquires a full version of a neural network, the neural network including internal elements for processing instances of input image data having a set of color channels. The processor then generates, from the neural network, a set of sub-networks, each sub-network being a separate copy of the neural network with the internal elements for processing at least one of the color channels in instances of input image data removed, so that each sub-network is configured for processing a different set of one or more color channels in instances of input image data. The processor next provides the sub-networks for processing instances of input image data—and may itself use the sub-networks for processing instances of input image data.

    Using redundant transactions to verify the correctness of program code execution
    50.
    发明授权
    Using redundant transactions to verify the correctness of program code execution 有权
    使用冗余事务来验证程序代码执行的正确性

    公开(公告)号：US09448933B2

    公开(公告)日：2016-09-20

    申请号：US14013252

    申请日：2013-08-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sudhanva Gurumurthi ,  Vilas Sridharan

    IPC: G06F11/14 ,  G06F12/08

    CPC classification number: G06F12/0811

    Abstract: In the described embodiments, a processor core (e.g., a GPU core) receives a section of program code to be executed in a transaction from another entity in a computing device. The processor core sends the section of program code to one or more compute units in the processor core to be executed in a first transaction and concurrently executed in a second transaction, thereby creating a “redundant transaction pair.” When the first transaction and the second transaction are completed, the processor core compares a read-set of the first transaction to a read-set of the second transaction and compares a write-set of the first transaction to a write-set of the second transaction. When the read-sets and the write-sets match and no transactional error condition has occurred, the processor core allows results from the first transaction to be committed to an architectural state of the computing device.

    Abstract translation: 在所描述的实施例中，处理器核心（例如，GPU核心）从计算设备中的另一个实体接收要在事务中执行的程序代码部分。 处理器核心将程序代码段发送到处理器核心中的一个或多个计算单元，以在第一事务中执行并在第二事务中同时执行，从而创建“冗余事务对”。当第一事务和第二事务 处理器核心将第一事务的读取集合与第二事务的读取集进行比较，并将第一事务的写入集合与第二事务的写入集进行比较。 当读取集合和写入集合匹配并且没有发生事务错误条件时，处理器核心允许来自第一事务的结果被提交到计算设备的架构状态。

Patent Agency Ranking