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    IN-BAND DE-DUPLICATION
    41.
    发明申请
    IN-BAND DE-DUPLICATION 审中-公开

    公开(公告)号：US20170242870A1

    公开(公告)日：2017-08-24

    申请号：US15590898

    申请日：2017-05-09

    Applicant: Amazon Technologies, Inc.

    Inventor： Nafea Bshara ,  Leah Shalev ,  Erez Izenberg ,  Georgy Machulsky ,  Ron Diamant

    IPC: G06F17/30

    CPC classification number: G06F16/1752 ,  G06F16/27 ,  G06F16/9014

    Abstract: A method for in-band de-duplication, the method may include receiving by a hardware accelerator, a received packet of a first sequence of packets that conveys a first data chunk; applying a data chunk hash calculation process on the received packet while taking into account a hash calculation result obtained when applying the data chunk hash calculation process on a last packet of the first sequence that preceded the received packet; wherein the calculating of the first data chunk hash value is initiated before a completion of a reception of the entire first data chunk by the hardware accelerator.

    Glitch-free clock multiplexer
    43.
    发明授权
    Glitch-free clock multiplexer 有权

    公开(公告)号：US09612611B1

    公开(公告)日：2017-04-04

    申请号：US14869349

    申请日：2015-09-29

    Applicant: Amazon Technologies, Inc.

    Inventor： Guy Nakibly ,  Usama Nassir ,  Saar Gross ,  Nafea Bshara ,  Barak Wasserstrom ,  Daniel Joseph Grey

    IPC: G06F1/08

    CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/12

    Abstract: In a system having a first clock domain with a first clock and a second clock domain with a second clock, the first and second clocks are monitored to determine whether one or both clocks are active. The first clock is selected to be an output clock if the first clock is active and the second clock is disabled irrespective of the clock selection signal. The second clock is selected to be the output clock if the second clock is active and the first clock is disabled irrespective of the clock selection signal. If both the first clock and the second clock are active, either the first clock or the second clock is selected according to a received clock selection signal.

    Flexible remote direct memory access
    46.
    发明授权
    Flexible remote direct memory access 有权

    公开(公告)号：US11892967B2

    公开(公告)日：2024-02-06

    申请号：US17901720

    申请日：2022-09-01

    Applicant: Amazon Technologies, Inc.

    Inventor： Erez Izenberg ,  Leah Shalev ,  Nafea Bshara ,  Guy Nakibly ,  Georgy Machulsky

    IPC: G06F15/167 ,  H04L69/22 ,  G06F16/22

    CPC classification number: G06F15/167 ,  G06F16/22 ,  H04L69/22

    Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

    Networked programmable logic service provider
    47.
    发明授权
    Networked programmable logic service provider 有权

    公开(公告)号：US11863406B2

    公开(公告)日：2024-01-02

    申请号：US17466944

    申请日：2021-09-03

    Applicant: Amazon Technologies, Inc.

    Inventor： Robert Michael Johnson ,  Nafea Bshara ,  Matthew Shawn Wilson

    IPC: H04L12/24 ,  G06F9/50 ,  G06F15/78 ,  H04L41/5054 ,  H04L41/50

    CPC classification number: H04L41/5054 ,  G06F9/50 ,  G06F15/7871 ,  H04L41/5096

    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a networked server environment. In one example, a system hosting a network service providing field programmable gate array (FPGA) services includes a network service provider configured to receive a request to implement application logic in a plurality of FPGAs, allocate a computing instance comprising the FPGAs in responses to receiving the request, produce configuration information for programming the FPGAs, and send the configuration information to an allocated computing instance. The system further includes a computing host that is allocated by the network service provider as a computing instance which includes memory, processors configured to execute computer-executable instructions stored in the memory, and the programmed FPGAs.

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