公开(公告)号：US11003616B1

公开(公告)日：2021-05-11

申请号：US15635078

申请日：2017-06-27

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Adi Habusha ,  Yaniv Shapira ,  Daniel Joseph Grey

IPC: G06F13/42 ,  G06F13/40

Abstract: In a computer comprising a plurality of integrated circuits (ICs), each IC may be connected to all other ICs via a respective point-to-point interconnect. A source IC divides the data to be transmitted to a destination IC for a transaction to generate multiple data cells so that each data cell includes a different portion of the data. The source IC transmits one of the data cells to the destination IC and remaining data cells to intermediate ICs, wherein an intermediate IC is an IC other than the source IC or the destination IC. The intermediate ICs forward the remaining data cells to the destination IC.

公开(公告)号：US09612611B1

公开(公告)日：2017-04-04

申请号：US14869349

申请日：2015-09-29

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Usama Nassir ,  Saar Gross ,  Nafea Bshara ,  Barak Wasserstrom ,  Daniel Joseph Grey

IPC: G06F1/08

CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/12

Abstract: In a system having a first clock domain with a first clock and a second clock domain with a second clock, the first and second clocks are monitored to determine whether one or both clocks are active. The first clock is selected to be an output clock if the first clock is active and the second clock is disabled irrespective of the clock selection signal. The second clock is selected to be the output clock if the second clock is active and the first clock is disabled irrespective of the clock selection signal. If both the first clock and the second clock are active, either the first clock or the second clock is selected according to a received clock selection signal.

公开(公告)号：US10198026B1

公开(公告)日：2019-02-05

申请号：US15475030

申请日：2017-03-30

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Usama Nassir ,  Saar Gross ,  Nafea Bshara ,  Barak Wasserstrom ,  Daniel Joseph Grey

IPC: G06F1/08 ,  G06F1/12

Abstract: In a system having a first clock domain with a first clock and a second clock domain with a second clock, the first and second clocks are monitored to determine whether one or both clocks are active. The first clock is selected to be an output clock if the first clock is active and the second clock is disabled irrespective of the clock selection signal. The second clock is selected to be the output clock if the second clock is active and the first clock is disabled irrespective of the clock selection signal. If both the first clock and the second clock are active, either the first clock or the second clock is selected according to a received clock selection signal.