公开(公告)号：US12164427B2

公开(公告)日：2024-12-10

申请号：US18187014

申请日：2023-03-21

Applicant: NXP B.V.

Inventor： Antoine Fabien Dubois

IPC: G06F12/08 ,  G06F12/0815 ,  G06F13/28 ,  G06F13/40

Abstract: An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.

公开(公告)号：US20240405013A1

公开(公告)日：2024-12-05

申请号：US18325503

申请日：2023-05-30

Applicant: NXP B.V.

Inventor： Gijs Jan de Raad ,  Guido Wouter Willem Quax

IPC: H01L27/02

Abstract: An electrostatic discharge circuit includes two or more GGNMOS transistors where each transistor includes two types of body contact regions. Body contact regions of one type are non substrate isolated from body contact regions of the other type. A body contact region of one type is electrically coupled to the source region of its transistor and a body contact region of the other type is electrically connected to at least one other body contact region of the same type of another GGNMOS transistor.

公开(公告)号：US20240402244A1

公开(公告)日：2024-12-05

申请号：US18204601

申请日：2023-06-01

Applicant: NXP B.V.

Inventor： Giorgio Carluccio ,  Björn Christian Brands ,  Henrik Asendorf

IPC: G01R31/28

Abstract: A two-stage test process for testing IC packages having integrated launchers includes a first stage in which an RF-accurate test process is used to perform RF-accurate tests on a sample set of IC packages to obtain RF-accurate test results and a loop-back test process is performed to obtain loop-back test results. Test characterization data is obtained by comparing the RF-accurate test results to the loop-back test results. In a second stage, larger-scale testing is performed solely with the loop-back test process, and the loop-back test results for each tested IC package are compared with the test characterization data to characterize the test operation of the tested IC package. The loop-back test process can employ a test jig employing a PCB-mounted or PCB-integrated loop-back structure for relatively rapid test setup and test processing.

公开(公告)号：US20240395737A1

公开(公告)日：2024-11-28

申请号：US18663503

申请日：2024-05-14

Applicant: NXP B.V.

Inventor： Ralph Matthijs van Schelven ,  Waqas Hassan Syed ,  Konstantinos Doris ,  Lukas Frederik Tiemeijer ,  Gilles Montoriol ,  Francis Jean Guy AUVRAY

IPC: H01L23/66 ,  H01L23/498

Abstract: A package for an integrated circuit, IC, the package comprising an interposer comprising: a first metal layer including a first metal plate; a second metal layer including a second metal plate; and a dielectric layer separating the first metal layer and the second metal layer, wherein the first metal plate and the second metal plate are arranged to form a parallel plate waveguide, PPW, and wherein the first metal plate comprises a slot for receiving one or more differential signals from the IC.

公开(公告)号：US20240393391A1

公开(公告)日：2024-11-28

申请号：US18360147

申请日：2023-07-27

Applicant: NXP B.V.

Inventor： Jorge Ernesto Perez Chamorro ,  Vasudev Srinivasan ,  Andreas Lentz ,  Jean-Michel Cioranesco

IPC: G01R31/317

Abstract: A fault detection system includes a state register, an error detection code (EDC) register, logic circuitry, an EDC generator, and an EDC checker. The state and EDC registers store first reference data and first checksum data, respectively. The logic circuitry executes a logic function based on the first reference data to iteratively generate second reference data that is different from the first reference data, and updates the first reference data of the state register with the second reference data of one iteration. The EDC generator iteratively generates second checksum data based on the iteratively generated second reference data and updates the first checksum data of the EDC register with the second checksum data of one iteration. The EDC checker detects a fault in the IC based on the updated first reference data and the updated first checksum data.

公开(公告)号：US20240388429A1

公开(公告)日：2024-11-21

申请号：US18319982

申请日：2023-05-18

Applicant: NXP B.V.

Inventor： Christine van Vredendaal ,  Melissa Azouaoui ,  Marcel Medwed ,  Tobias Schneider

IPC: H04L9/08 ,  H04L9/32

Abstract: A data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for generating keys in a hash based signature system in a processor, the instructions, including: generating, by a random number generator, a seed; repeatedly hashing the seed with a first hash function to produce n/k chained seeds, wherein n is a total number secret keys generated and k is a number of secret keys generated from each chained seed; and generating k secret keys from each of the n/k chained seeds using a second hash function, wherein at least one of the k secret keys is generated from another of the k secret keys in a sequential chain.

公开(公告)号：US20240388259A1

公开(公告)日：2024-11-21

申请号：US18638786

申请日：2024-04-18

Applicant: NXP B.V.

Inventor： Xin Yang ,  Stephane David ,  Mark Pieter van der Heijden ,  Dominicus MARTINUS WILHELMUS Leenaerts

IPC: H03F1/32 ,  H03F3/24

Abstract: A bias circuit for a RF amplifier is described. The bias circuit includes a first transistor and a second transistor configured as a first current mirror. A first current source is arranged between a supply node and the first transistor first terminal. An output of the bias circuit is coupled to the second transistor second terminal. A second current mirror coupled to the first current mirror and the bias circuit output. The bias circuit includes a first resistor coupled between a first transistor control terminal and a second transistor control terminal and a variable capacitor coupled between the second transistor control terminal and a ground.

公开(公告)号：US20240387271A1

公开(公告)日：2024-11-21

申请号：US18787368

申请日：2024-07-29

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Yufu Liu

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: Packaged semiconductor devices are disclosed, comprising: a semiconductor die having a top major surface with a plurality of contact pads thereon, and four sides, wherein the sides are stepped such that a lower portion of each side extends laterally beyond a respective upper portion; encapsulating material encapsulating the top major surface and the upper portion of each of the sides wherein the semiconductor die is exposed at the lower portion of each of the sides; a contact-redistribution structure on the encapsulating material over the top major surface of the semiconductor die; a plurality of metallic studs extending through the encapsulating material, and providing electrical contact between the contact pads and the contact-redistribution structure. Corresponding methods are also disclosed.

公开(公告)号：US20240385644A1

公开(公告)日：2024-11-21

申请号：US18352574

申请日：2023-07-14

Applicant: NXP B.V.

Inventor： Sagarkumar Jagdishkumar Patel ,  Sakshi Sharma ,  Ashutosh Kumar ,  Nidhi Puri ,  Love Gupta

IPC: G06F1/12 ,  G06F30/396

Abstract: Aspects of the subject disclosure address the traditional trade-off between performance and area, in relation to circuit and system design, together with power as an additional factor of consideration. Circuits and systems of this disclosure may realize a datapath of data in respect of memory state elements (e.g., registers, flops, etc.) that is dependent on multiple qualifiers. Aspects of this disclosure enhance (e.g., optimize) area and reduce leakage power associated with circuits and systems. Furthermore, aspects of this disclosure enable and enhance an insertion of clock-gating circuits or mechanisms to reduce dynamic-power consumption depending on states of the qualifiers.

公开(公告)号：US20240380372A1

公开(公告)日：2024-11-14

申请号：US18655916

申请日：2024-05-06

Applicant: NXP B.V.

Inventor： Frederic Darthenay

IPC: H03F3/45 ,  H03F1/26 ,  H03F3/00

Abstract: An amplifier circuit comprising: a first-stage residue-reduction storage unit; a final-stage residue-reduction storage unit; and a switching network. The switching network is operable to control the amplifier circuit according to the following operational configurations: a first residue-reduction configuration; a second residue-reduction configuration; and an operational configuration. Such an amplifier circuit uses a low number of residue-reduction steps to reduce global residual voltage to a very low level when the amplifier circuit is subsequently used in the operational configuration.