公开(公告)号：US20090283850A1

公开(公告)日：2009-11-19

申请号：US12346857

申请日：2008-12-31

Applicant: An-Thung Cho ,  Chia-Tien Peng ,  Kun-Chih Lin

Inventor： An-Thung Cho ,  Chia-Tien Peng ,  Kun-Chih Lin

IPC: H01L31/0224 ,  H01L21/00

CPC classification number: H01L31/0384 ,  H01L27/14667 ,  H01L27/14692 ,  H01L31/03921 ,  Y02E10/50

Abstract: An optical sensor includes a silicon-rich dielectric photosensitive device and a read-out device. The silicon-rich dielectric photosensitive device includes a first electrode, a second electrode, and a photosensitive silicon-rich dielectric layer disposed therebetween. The photosensitive silicon-rich dielectric layer includes a plurality of nanocrystalline silicon crystals therein. The read-out device is electrically connected to the first electrode of the silicon-rich dielectric photosensitive device for reading out opto-electronic signals transmitted from the photo-sensitive silicon-rich dielectric layer.

Abstract translation: 光学传感器包括富硅介电光敏器件和读出器件。 富含硅的电介质光敏元件包括第一电极，第二电极和位于它们之间的感光性富硅介电层。 感光性富硅介电层在其中包含多个纳米晶体硅晶体。 读出装置电连接到富硅电介质光敏装置的第一电极，用于读出从感光富硅电介质层传输的光电信号。

公开(公告)号：US07608475B2

公开(公告)日：2009-10-27

申请号：US11254303

申请日：2005-10-19

Applicant: Long-Sheng Liao ,  Kun-Chih Lin ,  Chia-Tien Peng

Inventor： Long-Sheng Liao ,  Kun-Chih Lin ,  Chia-Tien Peng

IPC: H01L21/00

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/2026 ,  H01L21/2205 ,  H01L21/268 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675

Abstract: A buffer layer for promoting electron mobility. The buffer layer comprises amorphous silicon layer (a-Si) and an oxide-containing layer. The a-Si has high enough density that the particles in the substrate are prevented by the a-Si buffer layer from diffusing into the active layer. As well, the buffer, having thermal conductivity, provides a good path for thermal diffusion during the amorphous active layer's recrystallization by excimer laser annealing (ELA). Thus, the uniformity of the grain size of the crystallized silicon is improved, and electron mobility of the TFT is enhanced.

Abstract translation: 用于促进电子迁移率的缓冲层。 缓冲层包括非晶硅层（a-Si）和含氧化物层。 a-Si具有足够高的密度，通过a-Si缓冲层防止衬底中的颗粒扩散到有源层中。 同样，具有导热性的缓冲器为通过受激准分子激光退火（ELA）的无定形有源层重结晶期间的热扩散提供了良好的途径。 因此，结晶硅的晶粒尺寸的均匀性提高，TFT的电子迁移率提高。

公开(公告)号：US20060038173A1

公开(公告)日：2006-02-23

申请号：US11254303

申请日：2005-10-19

Applicant: Long-Sheng Liao ,  Kun-Chih Lin ,  Chia-Tien Peng

Inventor： Long-Sheng Liao ,  Kun-Chih Lin ,  Chia-Tien Peng

IPC: H01L31/0376

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/2026 ,  H01L21/2205 ,  H01L21/268 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675

Abstract: A buffer layer for promoting electron mobility. The buffer layer comprises amorphous silicon layer (a-Si) and an oxide-containing layer. The a-Si has high enough density that the particles in the substrate are prevented by the a-Si buffer layer from diffusing into the active layer. As well, the buffer, having thermal conductivity, provides a good path for thermal diffusion during the amorphous active layer's recrystallization by excimer laser annealing (ELA). Thus, the uniformity of the grain size of the crystallized silicon is improved, and electron mobility of the TFT is enhanced.

公开(公告)号：US06700663B1

公开(公告)日：2004-03-02

申请号：US10248442

申请日：2003-01-21

Applicant: Kun-chih Lin

Inventor： Kun-chih Lin

IPC: G01J400

CPC classification number: H01L21/02686 ,  B23K26/032 ,  G01N21/211 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2026

Abstract: An amorphous silicon thin film is formed on a substrate first. Then the thin film is irradiated by a laser plus having an irradiation interval along a first direction to re-crystallize the thin film into a polysilicon thin film. A light source is thereafter focused into a micro spot having a diameter smaller than the irradiation interval, and the polysilicon thin film is irradiated by the micro spot moving along the first direction and having a relative moving distance to obtain a spectrum.

Abstract translation: 首先在基板上形成非晶硅薄膜。 然后，通过沿着第一方向具有照射间隔的激光加以照射薄膜，以使薄膜再结晶成多晶硅薄膜。 然后将光源聚焦成直径小于照射间隔的微点，并且通过沿着第一方向移动的微点照射多晶硅薄膜并具有相对移动距离以获得光谱。

公开(公告)号：US09136841B2

公开(公告)日：2015-09-15

申请号：US13561076

申请日：2012-07-29

Applicant: Kun-Chih Lin ,  Wen-Chi Wu

Inventor： Kun-Chih Lin ,  Wen-Chi Wu

IPC: G01R27/26 ,  H03K17/96 ,  G01D5/24

CPC classification number: H03K17/962 ,  G01D5/24 ,  H03K2217/96074 ,  H03K2217/960745

Abstract: A capacitance difference detecting circuit with a control circuit, a first capacitor, a second capacitor, a voltage control unit and a computing device. The control circuit generates a control signal according to a first voltage and a second voltage. The voltage control unit cooperates with the first capacitor to be detected and the second capacitor to be detected, according to the control signal, to generate the first voltage and the second voltage. The computing device computes a capacitance difference between the first capacitor to be detected and the second capacitor to be detected according to the first voltage, the second voltage and a parameter of the voltage control unit.

Abstract translation: 一种具有控制电路，第一电容器，第二电容器，电压控制单元和计算装置的电容差检测电路。 控制电路根据第一电压和第二电压产生控制信号。 电压控制单元根据控制信号与要检测的第一电容器和待检测的第二电容器协作以产生第一电压和第二电压。 计算装置根据第一电压，第二电压和电压控制单元的参数来计算待检测的第一电容器和待检测的第二电容器之间的电容差。

公开(公告)号：US20120286812A1

公开(公告)日：2012-11-15

申请号：US13561076

申请日：2012-07-29

Applicant: Kun-Chih Lin ,  Wen-Chi Wu

Inventor： Kun-Chih Lin ,  Wen-Chi Wu

IPC: G01R27/26

CPC classification number: H03K17/962 ,  G01D5/24 ,  H03K2217/96074 ,  H03K2217/960745

Abstract: A capacitance difference detecting circuit, which comprises: a control circuit, for generating a control signal according to a first voltage and a second voltage; a first capacitor to be detected; a second capacitor to be detected; a voltage control unit, for cooperating with the first capacitor to be detected and the second capacitor to be detected, according to the control signal, to generate the first voltage and the second voltage; and a computing device, for computing a capacitance difference between the first capacitor to be detected and the second capacitor to be detected according to the first voltage, the second voltage and a parameter of the voltage control unit.

Abstract translation: 一种电容差检测电路，包括：控制电路，用于根据第一电压和第二电压产生控制信号; 要检测的第一电容器; 要检测的第二电容器; 根据控制信号，与要检测的第一电容器和待检测的第二电容器配合的电压控制单元，以产生第一电压和第二电压; 以及计算装置，用于根据第一电压，第二电压和电压控制单元的参数来计算要检测的第一电容器和待检测的第二电容器之间的电容差。

公开(公告)号：US20120227782A1

公开(公告)日：2012-09-13

申请号：US13046471

申请日：2011-03-11

Applicant: Chin-Yao Tsai ,  Yu-Chun Peng ,  Po-Han Lin ,  Yi-Kai Lin ,  Chen-Liang Liao ,  Chih-Hsiung Chang ,  Kun-Chih Lin

Inventor： Chin-Yao Tsai ,  Yu-Chun Peng ,  Po-Han Lin ,  Yi-Kai Lin ,  Chen-Liang Liao ,  Chih-Hsiung Chang ,  Kun-Chih Lin

IPC: H01L31/05

CPC classification number: H01L31/05 ,  H01L31/0201 ,  H01L31/046 ,  Y02E10/50

Abstract: In one aspect of the present invention, a photovoltaic module includes a plurality of sub-modules. Each sub-module includes a plurality of photovoltaic cells spatially arranged as an array, each cell having first and second conductive layers sandwiching an active layer therebetween. The cells in each sub-module are electrically connected to each other in series. Each sub-module further includes positive and negative electrodes formed on the second conductive layers of the first and last cells, respectively, in a respective sub-module. The positive electrode of each sub-module is electrically connected to each other and the negative electrode of each sub-module is electrically connected to each other such that the plurality of sub-modules is electrically connected in parallel. The plurality of sub-modules is spatially arranged next to each other as an array such that at least one sub-module is spatially separated from its immediately next sub-module by a gap.

Abstract translation: 在本发明的一个方面，光伏组件包括多个子模块。 每个子模块包括空间上排列成阵列的多个光伏电池，每个电池具有夹在其间的活性层的第一和第二导电层。 每个子模块中的单元彼此串联电连接。 每个子模块还包括在相应的子模块中分别形成在第一和最后单元的第二导电层上的正极和负极。 每个子模块的正电极彼此电连接，并且每个子模块的负电极彼此电连接，使得多个子模块并联电连接。 多个子模块在空间上彼此相邻布置为阵列，使得至少一个子模块与其紧邻的下一个子模块在空间上与间隙分离。

公开(公告)号：US20110115502A1

公开(公告)日：2011-05-19

申请号：US12703732

申请日：2010-02-10

Applicant: Kun-Chih Lin ,  Wen-Chi Wu

Inventor： Kun-Chih Lin ,  Wen-Chi Wu

IPC: G01R27/26

CPC classification number: H03K17/962 ,  G01D5/24 ,  H03K2217/96074 ,  H03K2217/960745

Abstract: A capacitance difference detecting circuit, which comprises: a control circuit, for generating a control signal according to a first voltage and a second voltage; a first capacitor to be detected; a second capacitor to be detected; a first constant capacitor, having a terminal coupled to the first terminal of the first capacitor to be detected and the first input terminal; a second constant capacitor, having a terminal coupled to the first terminal of the second capacitor to be detected and the second input terminal; a voltage control unit, cooperating with the first capacitor to be detected, the second capacitor to be detected, the first constant capacitor and the second constant capacitor to control the first voltage and the second voltage. The voltage control unit is an adjustable capacitor and a capacitance value of the adjustable capacitor is controlled by the control signal.

Abstract translation: 一种电容差检测电路，包括：控制电路，用于根据第一电压和第二电压产生控制信号; 要检测的第一电容器; 要检测的第二电容器; 第一恒定电容器，具有耦合到待检测的第一电容器的第一端子和第一输入端子的端子; 第二恒定电容器，具有耦合到待检测的第二电容器的第一端子的端子和第二输入端子; 与待检测的第一电容器，待检测的第二电容器，第一恒定电容器和第二恒定电容器配合的电压控制单元，以控制第一电压和第二电压。 电压控制单元是可调电容器，可调电容器的电容值由控制信号控制。

公开(公告)号：US07745243B2

公开(公告)日：2010-06-29

申请号：US12416934

申请日：2009-04-02

Applicant: Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Kun-Chih Lin

Inventor： Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Kun-Chih Lin

IPC: H01L21/8232

CPC classification number: G02F1/133555 ,  G02F2001/136231

Abstract: A forming method of the present invention includes forming a first patterned conductive layer, which includes a transparent conductive layer and a metal layer stacked together on a substrate, where the first patterned conductive layer functions as gate lines, gate electrodes, common lines and predetermined transparent pixel electrode structures; and forming a second patterned conductive layer on the substrate. The second patterned conductive layer includes data lines and reflective pixel electrodes, and be directly connected to doping regions, such as source regions/drain regions. According to the forming method of the present invention, pixel structures of a transflective liquid crystal display device can be formed through five mask processes. Therefore, the manufacturing process of the transflective liquid crystal display device is effectively simplified, so the product yield is improved and the cost can be reduced.

Abstract translation: 本发明的形成方法包括形成第一图案化导电层，其包括在基板上堆叠在一起的透明导电层和金属层，其中第一图案化导电层用作栅极线，栅电极，共同线和预定透明 像素电极结构; 以及在所述衬底上形成第二图案化导电层。 第二图案化导电层包括数据线和反射像素电极，并且直接连接到诸如源极区/漏极区的掺杂区。 根据本发明的形成方法，可以通过五个掩模工艺形成半透射型液晶显示装置的像素结构。 因此，有效地简化了半透射型液晶显示装置的制造工艺，从而提高了产品成品率，降低了成本。

公开(公告)号：US20100006847A1

公开(公告)日：2010-01-14

申请号：US12241071

申请日：2008-09-30

Applicant: Chin-Wei Hu ,  Kun-Chih Lin

Inventor： Chin-Wei Hu ,  Kun-Chih Lin

IPC: H01L21/8238 ,  H01L29/786

CPC classification number: H01L27/1288 ,  H01L21/2652 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621

Abstract: A semiconductor device and the method for fabricating the same are disclosed. The fabrication method includes forming a PMOS device and an NMOS device on a substrate, wherein the PMOS device includes a first poly-silicon island, a gate dielectric layer covering the first poly-silicon island, and a first gate on the gate dielectric layer. The method of fabrication the PMOS device includes performing a P-type ion implantation process on the first poly-silicon island to form a plurality of P-type heavily doped regions and a plurality of P-type lightly doped regions. The length of the channel region is substantially less than 3 micron, and the length of at least one of the P-type lightly doped regions substantially is 10%-80% of the length of the channel region. The P-type lightly doped regions are used to improve the short channel effect of the PMOS device.

Abstract translation: 公开了一种半导体器件及其制造方法。 该制造方法包括在衬底上形成PMOS器件和NMOS器件，其中PMOS器件包括第一多晶硅岛，覆盖第一多晶硅岛的栅极电介质层和栅极介电层上的第一栅极。 制造PMOS器件的方法包括在第一多晶硅岛上执行P型离子注入工艺以形成多个P型重掺杂区域和多个P型轻掺杂区域。 沟道区的长度基本上小于3微米，并且P型轻掺杂区中的至少一个的长度基本上是沟道区长度的10％-80％。 P型轻掺杂区域用于改善PMOS器件的短沟道效应。