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    NITRIDE SEMICONDUCTOR DEVICE
    41.
    发明申请
    NITRIDE SEMICONDUCTOR DEVICE 审中-公开
    氮化物半导体器件

    公开(公告)号：US20110095335A1

    公开(公告)日：2011-04-28

    申请号：US13001825

    申请日：2009-07-02

    Applicant: Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Masahiro Hikita

    Inventor： Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Masahiro Hikita

    IPC: H01L29/06

    CPC classification number: H01L29/7787 ,  H01L29/0611 ,  H01L29/0661 ,  H01L29/1029 ,  H01L29/2003

    Abstract: A high breakdown voltage GaN-based transistor is provided on a silicon substrate. A nitride semiconductor device including: a silicon substrate, a SiO2 layer stacked on the silicon substrate and having a film thickness 100 nm or more; a silicon layer stacked on the SiO2 layer; a buffer layer stacked on the silicon layer; a GaN layer stacked on the buffer layer; an AlGaN layer stacked on the GaN layer; and a source electrode, a drain electrode, and a gate electrode that are formed on the AlGaN layer, and edge sidewalls of the silicon layer, the buffer layer, the GaN layer, and the AlGaN layer contact an increased-resistivity region.

    Abstract translation: 在硅衬底上提供高耐压GaN基晶体管。 一种氮化物半导体器件，包括：硅衬底，层叠在所述硅衬底上并具有100nm以上的膜厚度的SiO 2层; 层叠在SiO 2层上的硅层; 堆叠在所述硅层上的缓冲层; 堆叠在缓冲层上的GaN层; 堆叠在GaN层上的AlGaN层; 以及形成在AlGaN层上的源电极，漏电极和栅电极，硅层，缓冲层，GaN层和AlGaN层的边缘侧壁与增加电阻率的区域接触。

    Semiconductor device with Schottky and ohmic electrodes in contact with a heterojunction
    43.
    发明授权
    Semiconductor device with Schottky and ohmic electrodes in contact with a heterojunction 有权
    具有与异质结接触的肖特基和欧姆电极的半导体器件

    公开(公告)号：US07786511B2

    公开(公告)日：2010-08-31

    申请号：US12260383

    申请日：2008-10-29

    Applicant: Hidetoshi Ishida

    Inventor： Hidetoshi Ishida

    IPC: H01L29/12

    CPC classification number: H01L29/872 ,  H01L29/2003 ,  H01L29/205

    Abstract: To provide a semiconductor device that has a sufficiently low on-resistance and excellent low-capacitance and high-speed characteristics as compared with conventional GaN-based diodes. The semiconductor device includes: a substrate (101); a buffer layer (102); a stack structure (103 and 104) including at least one heterojunction unit (103 and 104) that is a stack of a layer (GaN layer 103) made of a nitride semiconductor and a layer (AlGaN layer 104) made of another nitride semiconductor having a larger band gap than the nitride semiconductor (GaN layer 103); a Schottky electrode (106) that is placed at a first end of the stack structure (103 and 104) and forms a Schottky barrier contact with the heterojunction unit (103 and 104); and an ohmic electrode (107) that is placed at a second end of the stack structure (103 and 104) and forms an ohmic contact with the heterojunction unit (103 and 104).

    Abstract translation: 为了提供与传统的GaN基二极管相比，具有足够低导通电阻和优异的低电容和高速特性的半导体器件。 半导体器件包括：衬底（101）; 缓冲层（102）; 包括至少一个异质结单元（103和104）的堆叠结构（103和104），其是由氮化物半导体制成的层（GaN层103）和由另一个氮化物半导体制成的层（AlGaN层104） 比氮化物半导体（GaN层103）更大的带隙; 放置在堆叠结构（103和104）的第一端并与异质结单元（103和104）形成肖特基势垒的肖特基电极（106）。 以及放置在堆叠结构（103和104）的第二端并与异质结单元（103和104）形成欧姆接触的欧姆电极（107）。

    Semiconductor device
    45.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060175618A1

    公开(公告)日：2006-08-10

    申请号：US11346266

    申请日：2006-02-03

    Applicant: Hidetoshi Ishida

    Inventor： Hidetoshi Ishida

    IPC: H01L33/00

    CPC classification number: H01L29/2003 ,  B82Y20/00 ,  G02B1/02 ,  H01L29/045 ,  H01L29/7787 ,  H01L33/16 ,  H01L33/20 ,  H01S5/2201 ,  H01S5/34333

    Abstract: A semiconductor device, which can accurately control carrier density, includes: a single crystal substrate; a semiconductor layer which is made of hexagonal crystal with 6 mm symmetry and is formed on the single crystal substrate; a source electrode, a drain electrode and a gate electrode which are formed on the semiconductor layer, where the main surfaces of a GaN layer and an AlGaN layer constituting the semiconductor layer respectively include C-axis of the hexagonal crystal, and a length direction of a channel region in the semiconductor layer is parallel to the C-axis of the hexagonal crystal.

    Abstract translation: 可以精确地控制载流子密度的半导体装置包括：单晶基板; 形成在单晶衬底上的由六边形晶体制成的对称6mm的半导体层; 形成在半导体层上的源电极，漏电极和栅电极，其中构成半导体层的GaN层和AlGaN层的主表面分别包括六方晶的C轴，长度方向 半导体层中的沟道区域平行于六方晶体的C轴。

    Field effect transistor and method for fabricating the same
    46.
    发明申请
    Field effect transistor and method for fabricating the same 有权
    场效应晶体管及其制造方法

    公开(公告)号：US20060124962A1

    公开(公告)日：2006-06-15

    申请号：US11297386

    申请日：2005-12-09

    Applicant: Tetsuzo Ueda ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

    Inventor： Tetsuzo Ueda ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

    IPC: H01L31/0328

    CPC classification number: H01L21/28581 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

    Abstract: A field effect transistor includes a first semiconductor layer made of a multilayer of a plurality of semiconductor films and a second semiconductor layer formed on the first semiconductor layer. A source electrode and a drain electrode are formed on the second semiconductor layer to be spaced from each other. An opening having an insulating film on its inner wall is formed in a portion of the second semiconductor layer sandwiched between the source electrode and the drain electrode so as to expose the first semiconductor layer therein. A gate electrode is formed in the opening to be in contact with the insulating film and the first semiconductor layer on the bottom of the opening.

    Abstract translation: 场效应晶体管包括由多个半导体膜的多层构成的第一半导体层和形成在第一半导体层上的第二半导体层。 源电极和漏电极形成在第二半导体层上以彼此间隔开。 在夹在源电极和漏极之间的第二半导体层的一部分中形成有在其内壁上具有绝缘膜的开口，以便在其中露出第一半导体层。 在开口部形成有与绝缘膜和开口底部的第一半导体层接触的栅电极。

    RF power amplifier
    49.
    发明授权
    RF power amplifier 有权

    公开(公告)号：US06621347B2

    公开(公告)日：2003-09-16

    申请号：US10017391

    申请日：2001-12-18

    Applicant: Shigeru Morimoto ,  Hidetoshi Ishida ,  Motonari Katsuno ,  Masahiro Maeda

    Inventor： Shigeru Morimoto ,  Hidetoshi Ishida ,  Motonari Katsuno ,  Masahiro Maeda

    IPC: H03F368

    CPC classification number: H03F3/601 ,  H03F3/193 ,  H03F3/265

    Abstract: An RF power amplifier has a pair of power amplifying elements for receiving first and second distributed signals resulting from distribution of an input signal from the outside and having the characteristics of the same amplitude and opposite phases, performing power amplification with respect to each of the first and second distributed signals that have been received, and outputting the first and second amplified signals and a pair of transmission lines connected correspondingly to the pair of power amplifying elements. The pair of transmission lines have a pair of protruding portions provided at respective edge portions thereof disposed in opposing relation. The pair of protruding portions are disposed in mutually spaced apart and opposing relation to compose a capacitor.

    Etchant and method for fabricating a semiconductor device using the same
    50.
    发明授权
    Etchant and method for fabricating a semiconductor device using the same 有权
    用于制造使用其的半导体器件的蚀刻剂和方法

    公开(公告)号：US06620738B2

    公开(公告)日：2003-09-16

    申请号：US09484473

    申请日：2000-01-18

    Applicant: Hidetoshi Ishida ,  Atsushi Noma ,  Daisuke Ueda

    Inventor： Hidetoshi Ishida ,  Atsushi Noma ,  Daisuke Ueda

    IPC: H01L21302

    CPC classification number: C09K13/08

    Abstract: An etchant for etching at least one of a titanium material and silicon oxide includes a mixed liquid of HCl, NH4F and H2O. When the etchant has a NH4F/HCl molar ratio of less than one, only the titanium material is etched. When the etchant has a NH4F/HCl molar ratio of more than one, only silicon oxide is etched. When the etchant has a NH4F/HCl molar ratio of one, the titanium material and silicon oxide are etched at the same rate.

    Abstract translation: 用于蚀刻钛材料和氧化硅中的至少一种的蚀刻剂包括HCl，NH 4 F和H 2 O的混合液体。 当蚀刻剂的NH 4 F / HCl摩尔比小于1时，仅蚀刻钛材料。 当蚀刻剂的NH4F / HCl摩尔比大于1时，仅刻蚀氧化硅。 当蚀刻剂的NH4F / HCl摩尔比为1时，以相同的速率蚀刻钛材料和氧化硅。

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