公开(公告)号：US07558101B1

公开(公告)日：2009-07-07

申请号：US11957366

申请日：2007-12-14

申请人： Hagop Nazarian ,  Michael Achter

发明人： Hagop Nazarian ,  Michael Achter

IPC分类号： G11C11/00 ,  G11C11/15 ,  G11C11/34

CPC分类号： G11C7/06 ,  G11C7/08 ,  G11C16/26 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50

摘要： Systems and methods for improving memory cell sensing margins by utilizing an optimal reference stimulus. A stimulus component applies a plurality of different reference stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the serially applied plurality of different reference stimuli. An analysis component computes an optimal reference stimulus by selecting one of the plurality of different reference stimuli, the one of the plurality of different reference stimuli associated with an absolute minima of number of memory cell characteristics that changed state as a function of the applied plurality of different reference stimuli.

摘要翻译： 通过利用最佳参考刺激来改善记忆细胞感受边缘的系统和方法。 刺激分量将多个不同的参考刺激应用于存储器件的多个存储单元。 感测组件根据串行应用的多个不同的参考刺激来感测多个存储器单元中的每个存储器单元的特性。 分析组件通过选择多个不同参考刺激中的一个来计算最佳参考刺激，所述多个不同参考刺激中的一个与根据应用的多个参考刺激的函数改变状态的存储器单元特性的绝对最小值的绝对最小值相关联 不同的参考刺激。

公开(公告)号：US20090154260A1

公开(公告)日：2009-06-18

申请号：US11957366

申请日：2007-12-14

申请人： Hagop Nazarian ,  Michael Achter

发明人： Hagop Nazarian ,  Michael Achter

IPC分类号： G11C7/00

CPC分类号： G11C7/06 ,  G11C7/08 ,  G11C16/26 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50

摘要： Systems and methods for improving memory cell sensing margins by utilizing an optimal reference stimulus. A stimulus component applies a plurality of different reference stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the serially applied plurality of different reference stimuli. An analysis component computes an optimal reference stimulus by selecting one of the plurality of different reference stimuli, the one of the plurality of different reference stimuli associated with an absolute minima of number of memory cell characteristics that changed state as a function of the applied plurality of different reference stimuli

摘要翻译： 通过利用最佳参考刺激来改善记忆细胞感受边缘的系统和方法。 刺激分量将多个不同的参考刺激应用于存储器件的多个存储单元。 感测组件根据串行应用的多个不同的参考刺激来感测多个存储器单元中的每个存储器单元的特性。 分析组件通过选择多个不同参考刺激中的一个来计算最佳参考刺激，所述多个不同参考刺激中的一个与根据应用的多个参考刺激的函数改变状态的存储器单元特性的绝对最小值的绝对最小值相关联 不同的参考刺激

公开(公告)号：US20090154234A1

公开(公告)日：2009-06-18

申请号：US11957309

申请日：2007-12-14

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26

摘要： Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and an overlapped bit distribution associated with the memory cell. Such mathematical operation can produce a resulting distribution that can facilitate identification by an analysis component of at least one overlapped bit distribution associated with cells of the one or more multi cell memory devices. Consequently, read errors associated with overlapped bits of a memory cell device can be mitigated.

摘要翻译： 这里描述了一个或多个多单元存储器件的重叠状态分布之间的区别。 作为示例，系统可以包括计算组件，其可以对所识别的非重叠位分布和与存储器单元相关联的重叠位分布执行数学运算。 这种数学运算可以产生结果分布，其可以促进由分析组件识别与一个或多个多单元存储器设备的单元相关联的至少一个重叠位分配。 因此，可以减轻与存储器单元装置的重叠位相关联的读取错误。

公开(公告)号：US20090109760A1

公开(公告)日：2009-04-30

申请号：US11929741

申请日：2007-10-30

申请人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

发明人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/12

摘要： Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell.

摘要翻译： 改进存储器件编程的系统和方法。 脉冲分量将不同的编程脉冲施加到存储单元。 分析组件根据应用的不同编程脉冲测量存储器单元的一个或多个特性的值。 计算组件根据存储单元的一个或多个特性的测量值来计算应用的不同编程脉冲。 分析组件测量存储器单元的一个或多个特性的一个或多个值，计算组件根据存储器单元的一个或多个特性的一个或多个测量值来计算一个或多个编程脉冲，以及 脉冲分量将一个或多个编程脉冲施加到存储器单元。

公开(公告)号：US20090109721A1

公开(公告)日：2009-04-30

申请号：US11929724

申请日：2007-10-30

申请人： Hagop Nazarian ,  Harry Kuo ,  Michael Achter

发明人： Hagop Nazarian ,  Harry Kuo ,  Michael Achter

IPC分类号： G11C5/06

CPC分类号： G11C8/14 ,  G11C8/08 ,  G11C16/0416 ,  G11C16/0491 ,  G11C16/10

摘要： An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines.

摘要翻译： 一种包括多对非易失性存储器（“NVM”）单元的二维或三维阵列的装置，其被耦合以使能NVM单元的编程和擦除。 多对NVM单元电连接到字线和位线。 每对NVM单元包括第一存储单元和第二存储单元。 第一和第二存储单元包括第一源极/漏极，第二源极/漏极和控制栅极。 第一存储单元的第一源极/漏极连接到位线之一。 第一存储单元的第二源极/漏极连接到第二存储单元的第一源极/漏极。 第二存储单元的第二源极/漏极连接到另一个位线。 第一和第二存储单元的控制栅极连接到不同的字线。

公开(公告)号：US20060193169A1

公开(公告)日：2006-08-31

申请号：US11065986

申请日：2005-02-25

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3427 ,  G11C2211/5648

摘要： The programming method of the present invention minimizes program disturb by initially programming cells on the same wordline with the logical state having the highest threshold voltage. The remaining cells on the wordline are programmed to their respective logical states in order of decreasing threshold voltage levels.

摘要翻译： 本发明的编程方法通过在具有最高阈值电压的逻辑状态的同一字线上最初编程单元来最小化程序干扰。 字线上的剩余单元按照降低阈值电压电平的顺序编程到它们各自的逻辑状态。

公开(公告)号：US20060044872A1

公开(公告)日：2006-03-02

申请号：US10933196

申请日：2004-09-02

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/30

摘要： NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize depletion mode floating gate memory cells. Depletion mode floating gate memory cells allow for increased cell current through lower channel rdS resistance and decreased “narrow width” effect, allowing for increased scaling of NAND memory cell strings. In addition, the required voltages for reading and programming operations are reduced, allowing the use of more efficient, lower voltage charge pumps and a reduction circuit element feature sizes and layouts. Cell inhibit of unselected cells is also increased, reducing the likelihood of cell disturb in the memory array. Operation speed is improved by increasing read current of the selected NAND string and by increasing the ability to overcome the RC time constants of circuit lines and capacitances through lowered voltage swings and increased current supplies.

摘要翻译： NAND架构描述了利用耗尽型浮动栅极存储器单元的闪存存储器串，存储器阵列和存储器件。 耗尽模式浮动栅极存储器单元允许通过较低通道电阻和较窄的“窄宽度”效应增加电池电流，从而允许增加NAND存储器单元串的缩放。 此外，读取和编程操作所需的电压降低，允许使用更有效，更低电压的电荷泵和降低电路元件特征尺寸和布局。 未选择的细胞的细胞抑制也增加，降低了存储器阵列中细胞干扰的可能性。 通过增加所选NAND串的读取电流并通过降低的电压摆幅和增加的电流供应来提高克服电路线和电容的RC时间常数的能力来提高操作速度。

公开(公告)号：US20060038550A1

公开(公告)日：2006-02-23

申请号：US10921465

申请日：2004-08-19

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G05F3/16

CPC分类号： G05F3/205 ,  Y10S323/901

摘要： An improved start-up circuit and method for self-bias circuits is described that applies a start-up voltage and current to a self-bias circuit to initialize its operation in its desired stable state. Once the self-bias circuit converges to its desired state of operation a start-up voltage reference/voltage clamping circuit shuts off current flow to the self-bias circuit and the start-up circuit enters a low power mode of operation to reduce its overall current and power draw. This allows for embodiments of the present invention to be utilized in portable and/or low power devices where low power consumption is of increased importance. In one embodiment of the present invention, a band-gap voltage reference circuit is initiated utilizing a start-up circuit.

摘要翻译： 描述了用于自偏置电路的改进的启动电路和方法，其将启动电压和电流施加到自偏置电路以将其操作初始化为其所需的稳定状态。 一旦自偏置电路收敛到其期望的操作状态，启动电压基准/电压钳位电路就切断到自偏压电路的电流，并且启动电路进入低功率运行模式以减小其整体 电流和功率消耗。 这允许将本发明的实施例用于低功耗增加重要性的便携式和/或低功率设备中。 在本发明的一个实施例中，利用启动电路启动带隙电压参考电路。

公开(公告)号：US20050254295A1

公开(公告)日：2005-11-17

申请号：US11183917

申请日：2005-07-19

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G11C11/00 ,  G11C11/15 ,  G11C11/16

CPC分类号： G11C13/004 ,  G11C11/16 ,  G11C2013/0057

摘要： A method and apparatus for sensing the resistance state of data in a resistance memory cell by using the voltage coefficient of the cell instead of only its resistance. A voltage potential is applied across the resistance memory cell allowing the voltage coefficient of the cell to be determined and subsequently used to determine the logic state of the cell.

摘要翻译： 一种用于通过使用电池的电压系数而不是仅仅其电阻来感测电阻存储器单元中的数据的电阻状态的方法和装置。 电压电位施加在电阻存储器单元上，允许确定单元的电压系数，并随后用于确定单元的逻辑状态。

公开(公告)号：US20050057966A1

公开(公告)日：2005-03-17

申请号：US10663277

申请日：2003-09-16

申请人： Hagop Nazarian

发明人： Hagop Nazarian

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/12

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： A boosted substrate tub/substrate floating gate memory cell programming process is described that applies a voltage to the substrate or substrate “tub” of a NAND Flash memory array to precharge a channel of carriers within the floating gate memory cells prior to applying a high gate programming voltage to the gate of the selected floating gate memory cells and coupling a program or program-inhibit voltage to program the selected floating gate memory cell(s) as desired. The use of a boosted tub programming approach avoids the requirement that the bitline and/or source line circuit design of the NAND Flash array be able to withstand or carry high voltages during programming of a floating gate memory cells and allows reuse of the block erase high voltage circuits connected to the substrate tub. This allows the NAND Flash memory array to be designed with smaller circuit designs and/or smaller circuit feature elements.