公开(公告)号：US06489906B2

公开(公告)日：2002-12-03

申请号：US09785552

申请日：2001-02-20

Applicant: Masahiro Matsumoto ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Keiji Hanzawa

Inventor： Masahiro Matsumoto ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Keiji Hanzawa

IPC: H03M300

CPC classification number: H03M3/484 ,  H03M3/474

Abstract: A &Dgr;&Sgr; type AD converter includes a local D/A converter having a SC integrator which is constructed by an analog switch operated at the first and second timings of an input 1, an analog switch operated at the first and second timings of an input 2, an analog switch operated at the first and second timings without selection of the input, a capacitor charged and discharged by these analog switches and an operational amplifier (21), a comparator (22), a D-type flip-flop (28), a switch (29) and reference voltage sources (30, 31).

Abstract translation: DELTASIGMA型AD转换器包括具有SC积分器的本地D / A转换器，该SC积分器由在输入端1的第一和第二定时操作的模拟开关，在输入端2的第一和第二定时操作的模拟开关， 在第一和第二定时操作的模拟开关，不选择输入，由这些模拟开关充电和放电的电容器和运算放大器（21），比较器（22），D型触发器（28）， 开关（29）和参考电压源（30,31）。

公开(公告)号：US06462580B2

公开(公告)日：2002-10-08

申请号：US09749474

申请日：2000-12-28

Applicant: Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

Inventor： Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

IPC: H03K19096

CPC classification number: H03K3/3565 ,  H03K19/018521

Abstract: The object of the present invention to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.

Abstract translation: 本发明的目的是提供一种半导体集成电路器件，其中使得输入信号具有低振幅以缩短输入信号的转换时间，所述集成电路器件以低功耗工作，而不流过突破电流， 尽管输入具有低幅度操作的输入信号，并且所述集成电路器件包括门电路，存储器和处理器。 当通过NMOS传输晶体管提供输入信号时，所述输入信号被输入到第一NMOS晶体管的栅极，并且同时被输入到与所述第一NMOS晶体管执行互补操作的第一PMOS晶体管的栅极 通过第二NMOS晶体管; 所述第一PMOS栅极通过第二PMOS晶体管连接到电源电位，并且所述第二NMOS晶体管的栅极连接到电源电位; 其中所述第二PMOS晶体管栅极的栅极由与所述第一NMOS晶体管的漏极和所述第一PMOS晶体管的漏极连接的信号控制。

公开(公告)号：US06385755B1

公开(公告)日：2002-05-07

申请号：US09613276

申请日：2000-07-10

Applicant: Tetsuya Shimomura ,  Fumio Murabayashi ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Takashi Hotta

Inventor： Tetsuya Shimomura ,  Fumio Murabayashi ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Takashi Hotta

IPC: G11C2900

CPC classification number: G06F11/1637 ,  G06F11/1654 ,  G06F11/2025 ,  G06F11/2038 ,  G06F11/2043

Abstract: An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.

Abstract translation: 信息处理系统具有多个处理器电路，每个处理器电路包括内部电路和内部处理结果输出电路，该系统具有连接到每个处理器电路的内部数据选择电路和至少一个故障检测电路。 每个处理器电路的内部处理结果输出电路输出由处理器电路中的各个内部电路处理的各个结果数据。 每个内部数据选择电路在预定的定时选择并输出从每个处理器电路的内部处理结果输出电路输出的一个选择的结果数据。 故障检测电路输出由处理器电路的各个内部数据选择电路选择的数据或由处理器电路在每个预定定时输出的数据之间的比较结果。

公开(公告)号：US06282136B1

公开(公告)日：2001-08-28

申请号：US09578854

申请日：2000-05-26

Applicant: Kohei Sakurai ,  Tatsumi Yamauchi ,  Masahiro Matsumoto ,  Fumio Murabayashi ,  Hiromichi Yamada ,  Atsushi Miyazaki ,  Keiji Hanzawa

Inventor： Kohei Sakurai ,  Tatsumi Yamauchi ,  Masahiro Matsumoto ,  Fumio Murabayashi ,  Hiromichi Yamada ,  Atsushi Miyazaki ,  Keiji Hanzawa

IPC: G11C700

CPC classification number: G11C7/1072 ,  G11C7/12 ,  G11C8/00

Abstract: In a semiconductor memory device, the drain of a transistor for pre-charging is connected to a data line via the Y switch. Lower level bit signals are input into an X decoder for selecting the word line in a memory cell array; and higher level bit signals are input into a Y decoder for selecting the Y switch control signal lines. The addresses in the memory cell array are arranged sequentially in the direction of the data lines.

Abstract translation: 在半导体存储器件中，用于预充电的晶体管的漏极经由Y开关连接到数据线。 低电平位信号被输入到用于选择存储单元阵列中的字线的X解码器中; 并且较高电平位信号被输入到用于选择Y开关控制信号线的Y解码器中。 存储单元阵列中的地址在数据线的方向上顺序排列。

公开(公告)号：US06172532B2

公开(公告)日：2001-01-09

申请号：US08925428

申请日：1997-09-08

Applicant: Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

Inventor： Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

IPC: H03K190948

CPC classification number: H03K3/3565 ,  H03K19/018521

Abstract: The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.

公开(公告)号：US5903503A

公开(公告)日：1999-05-11

申请号：US979811

申请日：1997-11-25

Applicant: Tatsumi Yamauchi ,  Fumio Murabayashi

Inventor： Tatsumi Yamauchi ,  Fumio Murabayashi

IPC: G06F9/38 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  H03K19/096 ,  G11C7/00

CPC classification number: G11C7/106 ,  G06F9/3869 ,  G11C7/1051 ,  G11C7/12 ,  G11C7/22 ,  H03K19/096

Abstract: A semiconductor integrated circuit device using precharge circuits free from the influence of a phase difference skew is provided. Each of the precharge circuits is controlled by a clock signal such that an arbitrary node in the circuit is precharged during a low level period or a high level period of the clock signal and the precharge circuit is operative during a high level period or a low level period of the clock signal. A first precharge circuit and a second precharge circuit having the same operational functions are arranged in parallel, and controlled by their respective clock signals to perform complementary operations, wherein the second precharge circuit is in an active period when the first precharge circuit is in a precharge period, and the second precharge circuit is in a precharge period when the first precharge circuit is in an active period.

Abstract translation: 提供了一种使用不受相位偏斜影响的预充电电路的半导体集成电路器件。 每个预充电电路由时钟信号控制，使得电路中的任意节点在时钟信号的低电平期间或高电平期间被预充电，并且预充电电路在高电平期间或低电平期间工作 时钟信号的周期。 具有相同操作功能的第一预充电电路和第二预充电电路并联布置并由它们各自的时钟信号进行控制以进行互补操作，其中当第一预充电电路处于预充电时，第二预充电电路处于有效期 期间，第二预充电电路处于第一预充电电路处于活动期间的预充电期间。

公开(公告)号：US5742550A

公开(公告)日：1998-04-21

申请号：US753019

申请日：1996-11-19

Applicant: Tatsumi Yamauchi ,  Fumio Murabayashi

Inventor： Tatsumi Yamauchi ,  Fumio Murabayashi

IPC: G06F9/38 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  H03K19/096 ,  G11C7/00

CPC classification number: G11C7/106 ,  G06F9/3869 ,  G11C7/1051 ,  G11C7/12 ,  G11C7/22 ,  H03K19/096

Abstract: A semiconductor integrated circuit device using precharge circuits free from the influence of a phase difference skew is provided. Each of the precharge circuits is controlled by a clock signal such that an arbitrary node in the circuit is precharged during a low level period or a high level period of the clock signal and the precharge circuit is operative during a high level period or a low level period of the clock signal. A first precharge circuit and a second precharge circuit having the same operational functions are arranged in parallel, and controlled by their respective clock signals to perform complementary operations, wherein the second precharge circuit is in an active period when the first precharge circuit is in a precharge period, and the second precharge circuit is in a precharge period when the first precharge circuit is in an active period.

公开(公告)号：US5539686A

公开(公告)日：1996-07-23

申请号：US315591

申请日：1994-09-30

Applicant: Fumio Murabayashi ,  Takashi Hotta ,  Masahiro Iwamura ,  Akiyoshi Osumi

Inventor： Fumio Murabayashi ,  Takashi Hotta ,  Masahiro Iwamura ,  Akiyoshi Osumi

IPC: H03K19/013 ,  H03K19/0175 ,  H03K19/018 ,  G06F7/50

CPC classification number: H03K19/013 ,  H03K19/017518 ,  H03K19/01806

Abstract: A carry propagating device, provided on a single substrate, is constituted by groups of first and second MOS transistors, a third MOS transistor, a bipolar transistor and first and second impedance elements. An output of the carry propagating device is provided at the collector of the bipolar transistor and is connected to a first power supply terminal through the first impedance element, the emitter is connected to a second power supply terminal through the second impedance element, and the base is connected to a fixed potential source. The first MOS transistors are connected in series between the emitter of the bipolar transistor and the second power supply terminal through the third MOS transistor controlled by a carry signal. As to the second MOS transistors, one is connected in parallel to the second impedance element and each of the remaining ones is connected between a common connection of a respective pair of adjacent ones of the series-connected first MOS transistors and the second power supply terminal. There is thus effected a speed-up of the carry signal and thereby a speeding-up of the signal processing. There is also provided a wiring scheme for preventing noise interference between different wirings. Moreover, a device has been schemed for a plurality of logic circuit blocks and including a data signal path for interconnecting different logic circuit blocks and facilitating the interfacing of a current-driven signal.

Abstract translation: 设置在单个基板上的携带传播装置由第一和第二MOS晶体管，第三MOS晶体管，双极晶体管和第一和第二阻抗元件组构成。 进位传播装置的输出设置在双极晶体管的集电极处，并通过第一阻抗元件连接到第一电源端子，发射极通过第二阻抗元件连接到第二电源端子，基极 连接到固定电位源。 第一MOS晶体管通过由进位信号控制的第三MOS晶体管串联连接在双极晶体管的发射极和第二电源端子之间。 对于第二MOS晶体管，一个与第二阻抗元件并联连接，其余的每个连接在一对相邻的串联连接的第一MOS晶体管和第二电源端子的公共连接 。 因此，进行了进位信号的加速，从而加速了信号处理。 还提供了用于防止不同布线之间的噪声干扰的布线方案。 此外，已经针对多个逻辑电路块设计了一种器件，并且包括用于互连不同逻辑电路块的数据信号路径，并且有助于电流驱动信号的接口。

公开(公告)号：US5412262A

公开(公告)日：1995-05-02

申请号：US279626

申请日：1994-07-25

Applicant: Yoji Nishio ,  Fumio Murabayashi ,  Kozaburo Kurita ,  Masahiro Iwamura

Inventor： Yoji Nishio ,  Fumio Murabayashi ,  Kozaburo Kurita ,  Masahiro Iwamura

IPC: H03K19/00 ,  H01L27/02 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/02

CPC classification number: H03K19/017527 ,  H03K19/018521 ,  H01L27/0214

Abstract: In a system wherein a plurality of semiconductor integrated circuit devices are coexistent and wherein a plurality of supply potential lines are laid, the main power sources of a TTL interface LSI and an ECL interface LSI are shared so as to reduce the number of supply potential lines. Besides, in a case where an LSI, for example, BiCMOS LSI to interface with both the TTL and ECL interface LSI's has a device withstand voltage of about 3 V, it is permitted to interface with both the LSI's across the supply voltage .vertline.5 V.vertline. of the main power source of the TTL interface LSI and the supply voltage .vertline.2 V.vertline. of the power source of the emitter follower portion of the ECL interface LSI because the supply voltages have a difference of 3 V.

Abstract translation: 在其中多个半导体集成电路器件共存并且其中布置多条电源线的系统中，TTL接口LSI和ECL接口LSI的主电源被共享，以便减少电源电位线的数量 。 此外，在与例如TTL和ECL接口LSI接口的BiCMOS LSI的LSI具有约3V的器件耐受电压的情况下，允许与两者的两端的电源电压| 5V | 的TTL接口LSI的主电源和电源电压| 2 V | 由于电源电压具有3V的差异，所以ECL接口LSI的射极跟随器部分的电源。

公开(公告)号：US5001365A

公开(公告)日：1991-03-19

申请号：US325911

申请日：1989-03-20

Applicant: Fumio Murabayashi ,  Yoji Nishio ,  Shoichi Kotoku ,  Kozaburo Kurita ,  Kazuo Kato

Inventor： Fumio Murabayashi ,  Yoji Nishio ,  Shoichi Kotoku ,  Kozaburo Kurita ,  Kazuo Kato

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/82 ,  H01L27/06 ,  H01L27/118 ,  H01L29/732 ,  H03K17/04 ,  H03K17/16 ,  H03K17/567 ,  H03K19/00 ,  H03K19/003 ,  H03K19/08 ,  H03K19/0944

CPC classification number: H01L27/0623 ,  H03K19/001 ,  H03K19/00353 ,  H03K19/09448

Abstract: A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal. In order to improve the operating speed, a potential difference reducing element is provided having a current path between its paired main terminals coupled between the first power source terminal and the output terminal for reducing the potential difference, which is present between the first power source terminal and the output terminal based on the base-emitter forward voltage of the bipolar transistor when the bipolar transistor is ON.

Abstract translation: 提供了具有集成在半导体衬底上的多个逻辑电路的半导体集成电路器件，其可以以基本上小于5V的电源电位差工作。逻辑电路包括具有基极和其集电极 - 发射极电流路径的双极晶体管 耦合在第一电源端子和输出端子之间，以及至少一个具有栅极的场效应晶体管，其响应于施加到输入端子的输入信号及其耦合在第一电源端子和基极之间的源极 - 漏极电流路径 的双极晶体管。 还提供半导体开关装置，其响应于施加到输入端子的输入信号，用于执行与双极晶体管的导通/截止操作互补的ON / OFF操作，并且在其双绞主端子之间具有电流通路 输出端子和第二电源端子。 为了提高工作速度，提供了一个电位差降低元件，其具有耦合在第一电源端子和输出端子之间的成对主端子之间的电流路径，用于减小电位差，该电位差存在于第一电源端子 以及当双极晶体管导通时基于双极晶体管的基极 - 发射极正向电压的输出端子。