公开(公告)号：US5890163A

公开(公告)日：1999-03-30

申请号：US721556

申请日：1996-09-26

Applicant: William Gregory Todd

Inventor： William Gregory Todd

IPC: G06F17/30 ,  G06Q10/10

CPC classification number: G06F17/30067 ,  G06Q10/107 ,  Y10S707/99953

Abstract: An electronic mail archiver for use in a computer system includes a user interface that allows a user to identify an electronic mail message to be archived from an electronic mail system, and a message transfer component that automatically retrieves the message from the electronic mail system in an electronic mail format and stores the message in a format defined by a data processing application capable of running in the computer system.

Abstract translation: 一种在计算机系统中使用的电子邮件归档器包括允许用户识别要从电子邮件系统存档的电子邮件消息的用户界面，以及从电子邮件系统自动检索消息的消息传送组件 电子邮件格式，并以能够在计算机系统中运行的数据处理应用程序定义的格式存储消息。

公开(公告)号：US5878237A

公开(公告)日：1999-03-02

申请号：US893849

申请日：1997-07-11

Applicant: Sompong P. Olarig

Inventor： Sompong P. Olarig

IPC: G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4013

Abstract: A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of peripheral component interconnect ("PCI") buses capable of operating at 66 MHz. Each of the plurality of PCI buses have the same logical bus number. The core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device connected to the plurality of PCI physical buses. Each of the plurality of PCI buses has its own read and write queues to provide transaction concurrency of PCI devices on different ones of the plurality of PCI buses when the transaction addresses are not the same or are M byte aligned. Upper and lower memory address range registers store upper and lower memory addresses associated with each PCI device. Whenever a transaction occurs, the transaction address is compared with the stored range of memory addresses. If a match between addresses is found then strong ordering is used. If no match is found then weak ordering may be used to improve transaction latency times. PCI device to PCI device transactions may occur without being starved by CPU host bus to PCI bus transactions.

Abstract translation: 集成在计算机系统中的核心逻辑芯片提供处理器主机和存储器总线之间的桥梁以及能够以66MHz工作的多个外围部件互连（“PCI”）总线。 多个PCI总线中的每一个具有相同的逻辑总线号。 核心逻辑芯片组具有针对连接到多个PCI物理总线的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线的仲裁器。 多个PCI总线中的每一个具有其自己的读取和写入队列，以便当交易地址不相同或是M字节对齐时，在多个PCI总线的不同的PCI总线上提供PCI设备的事务并发。 上下存储器地址范围寄存器存储与每个PCI设备相关联的上部和下部存储器地址。 每当事务发生时，将交易地址与存储的存储器地址范围进行比较。 如果发现地址之间的匹配，则使用强排序。 如果没有找到匹配，则可以使用弱排序来提高事务延迟时间。 PCI设备到PCI设备事务可能会发生，而不会被CPU主机总线淹没到PCI总线事务。

公开(公告)号：US5864607A

公开(公告)日：1999-01-26

申请号：US702899

申请日：1996-08-23

Applicant: P. Bradley Rosen ,  Lee D. Weinstein ,  George Favaloro ,  John A. Kowalonek ,  Benjamin Chigier ,  James A. Goldstein ,  Thomas C. Purcell ,  Glen R. Dash ,  David E. Winston ,  Michael A. Bromberg

Inventor： P. Bradley Rosen ,  Lee D. Weinstein ,  George Favaloro ,  John A. Kowalonek ,  Benjamin Chigier ,  James A. Goldstein ,  Thomas C. Purcell ,  Glen R. Dash ,  David E. Winston ,  Michael A. Bromberg

IPC: H04M1/27 ,  H04M1/723 ,  H04M1/82 ,  H04M3/493 ,  H04M3/527 ,  H04M11/00

CPC classification number: H04M3/527 ,  H04M1/723 ,  H04M1/82 ,  H04M3/4938 ,  H04M1/271 ,  H04M2201/40 ,  H04M7/0021

Abstract: A telephone system having a telephone network line for connection to an external phone line. The telephone system also includes a computer system and a telephone coupled to the telephone network line, and the telephone is taken off-hook to enter a voice command. A transmitter communicates the voice command from the telephone to the computer system without the telephone seizing the external phone line. A computer interface unit is connected to the computer system to receive the voice transmitted from the telephone and to transmit voice signals transmitted by the computer system to the telephone. A phone interface unit is connected between the telephone and telephone network line, and the phone interface unit is selectable between a first mode and a second mode. The phone interface unit connects the telephone to the telephone network line if it is in the first mode, and isolates the telephone from the telephone network line if it is in the second mode. If an external phone call is detected from the external phone line, the phone interface unit can be selected to be in the first mode if the external call is present. The computer system includes communication software for controlling communication in the telephone system, including receiving a voice command transmitted from the telephone when the telephone is off-hook, and controlling the phone interface unit to isolate the telephone from the external phone line when receiving the voice command from the telephone line.

Abstract translation: 具有用于连接到外部电话线路的电话网络线路的电话系统。 电话系统还包括计算机系统和耦合到电话网络线路的电话，并且电话摘机以进入语音命令。 发射机将语音命令从电话传送到计算机系统，而不用电话抓住外部电话线路。 计算机接口单元连接到计算机系统以接收从电话发送的语音，并将由计算机系统发送的语音信号传送到电话。 电话接口单元连接在电话和电话网络线之间，电话接口单元可在第一模式和第二模式之间选择。 电话接口单元如果处于第一模式，则将电话连接到电话网络线路，如果处于第二模式则将电话与电话网络线隔离。 如果从外部电话线检测到外部电话呼叫，则如果外部呼叫存在，则可以将电话接口单元选择为处于第一模式。 计算机系统包括用于控制电话系统中的通信的通信软件，包括当电话摘机时接收从电话发送的语音命令，以及控制电话接口单元在接收到语音时将电话与外部电话线隔离 命令从电话线。

公开(公告)号：US5841990A

公开(公告)日：1998-11-24

申请号：US760302

申请日：1996-12-04

Applicant: Jose J. Picazo, Jr. ,  Paul Kakul Lee ,  Robert P. Zager

Inventor： Jose J. Picazo, Jr. ,  Paul Kakul Lee ,  Robert P. Zager

IPC: G06F13/00 ,  H04L12/24 ,  H04L12/44 ,  H04L12/46 ,  H04L12/56 ,  H04L29/06 ,  H04J3/02

CPC classification number: H04L41/26 ,  H04L12/44 ,  H04L12/4616 ,  H04L12/462 ,  H04L12/4625 ,  H04L29/06 ,  H04L41/0213 ,  H04L41/046 ,  H04L49/351 ,  H04L49/90 ,  H04L49/901 ,  H04L63/0209 ,  H04L63/083 ,  H04L49/201 ,  H04L49/25 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/357 ,  H04L49/557

Abstract: A hub circuit with an integrated bridge circuit carried out in software including a switch for bypassing the bridge process such that the two bridged networks effectively become one network. An in-band management process in software is disclosed which receives and executes network management commands received as data packets from the LANs coupled to the integrated hub/bridge. Also, hardware and software to implement an isolate mode where data packets which would ordinarily be transferred by the bridge process are not transferred except in-band management packets are transferred to the in-band management process regardless of which network from which they arrived. Also disclosed, a packet switching machine having shared high-speed memory with multiple ports, one port coupled to a plurality of LAN controller chips coupled to individual LAN segments and an Ethernet microprocessor that sets up and manages a receive buffer for storing received packets and transferring pointers thereto to a main processor. The main processor is coupled to another port of the memory and analyzes received packets for bridging to other LAN segments or forwarding to an SNMP agent. The main microprocessor and the Ethernet processor coordinate to manage the utilization of storage locations in the shared memory. Another port is coupled to an uplink interface to higher speed backbone media such as FDDI, ATM etc. Speeds up to media rate are achieved by only moving pointers to packets around in memory as opposed to the data of the packets itself. A double password security feature is also implemented in some embodiments to prevent accidental or intentional tampering with system configuration settings.

公开(公告)号：US5841446A

公开(公告)日：1998-11-24

申请号：US742881

申请日：1996-11-01

Applicant: Dayang Dai

Inventor： Dayang Dai

IPC: G09G5/39 ,  G09G5/00

CPC classification number: G09G5/39 ,  G09G2360/122

Abstract: The present invention is a graphics subsystem with a plurality of storage elements addressed by multiple bit physical addresses and a video display with a plurality of pixels addressed by multiple bit logical addresses. The graphics subsystem includes an address conversion circuitry for converting the logical addresses of the pixels to physical addresses in the video memory. When the number of bytes needed to address the plurality of pixels across the screen is not equal to an integral power of two and the logical addresses of the plurality of pixels are arranged in tiles, the address conversion circuitry converts the logical addresses of the pixels to physical addresses in the video memory by converting only portions of the total address space into tiles at any one time.

Abstract translation: 本发明是具有由多个位物理地址寻址的多个存储元件和具有由多位逻辑地址寻址的多个像素的视频显示的图形子系统。 图形子系统包括用于将像素的逻辑地址转换为视频存储器中的物理地址的地址转换电路。 当在屏幕上寻址多个像素所需的字节数不等于2的整数倍并且多个像素的逻辑地址被排列成瓦片时，地址转换电路将像素的逻辑地址转换为 物理地址通过仅将地址空间的一部分转换成瓦片在任何一个时间。

公开(公告)号：US5640689A

公开(公告)日：1997-06-17

申请号：US414759

申请日：1995-03-31

Applicant: Markku J. Rossi

Inventor： Markku J. Rossi

IPC: H01Q1/08 ,  H04B1/38

CPC classification number: H04B1/3833 ,  H01Q1/084

Abstract: An electronic device includes a host component having a first antenna; and a radio unit that may be connected to the host component and that has a second, rotatable antenna. The radio unit also includes a switch that is triggered by rotation of the second antenna to activate either the first antenna or the second antenna.

Abstract translation: 电子设备包括具有第一天线的主机组件; 以及可以连接到主机组件并且具有第二可旋转天线的无线电单元。 无线电单元还包括由第二天线的旋转触发的开关，以激活第一天线或第二天线。

公开(公告)号：US5625535A

公开(公告)日：1997-04-29

申请号：US502198

申请日：1995-07-13

Applicant: David A. Hulsebosch ,  Richard A. Faulk

Inventor： David A. Hulsebosch ,  Richard A. Faulk

IPC: G06F1/16 ,  G06F1/18 ,  G06F1/20 ,  H05K7/20

CPC classification number: G06F1/1616 ,  G06F1/1635 ,  G06F1/1658 ,  G06F1/182 ,  G06F1/203

Abstract: A power supply module for a portable computer and a method of dissipating heat generated in the power supply module. The module comprises: (1) a circuit board having a plurality of power supply components mounted thereon, (2) a module electromagnetic shield at least partially surrounding the circuit board, the module electromagnetic shield electromagnetically shielding at least some of the plurality of power supply components, (3) metallic heat conduction paths, integrally disposed within the circuit board and substantially within a footprint of selected ones of the plurality of power supply components, for transferring heat from the selected ones of the plurality of power supply components through the circuit board and (4) compliant heat conduction pads, coupled between the circuit board and the module electromagnetic shield, for transferring the heat from the heat conduction paths to the module electromagnetic shield, the module electromagnetic shield dissipating the heat and thereby functioning as a heat sink, the heat conduction paths and heat conduction pads cooperating to form a compact structure for transferring heat from the selected ones of the plurality of power supply components to thereby reduce a required volume of the power supply module.

Abstract translation: 一种用于便携式计算机的电源模块和一种耗散在电源模块中产生的热量的方法。 该模块包括：（1）具有安装在其上的多个电源组件的电路板，（2）至少部分地围绕电路板的模块电磁屏蔽，所述模块电磁屏蔽电磁屏蔽所述多个电源 组件，（3）金属热传导路径，整体地设置在电路板内并且基本上在多个电源组件中的选定的电源组件的覆盖区内，用于从多个电源组件中的选定的电源组件通过电路板传送热量 和（4）耦合在电路板和模块电磁屏蔽之间的兼容热传导垫，用于将热量从热传导路径传递到模块电磁屏蔽，模块电磁屏蔽件散热并因此用作散热器， 热传导路径和热传导垫协作形成紧凑的结构 用于从所述多个电源组件中的所选择的电源组件传送热量，从而减少所述电源模块的所需体积。

公开(公告)号：US5590316A

公开(公告)日：1996-12-31

申请号：US445184

申请日：1995-05-19

Applicant: Brian S. Hausauer

Inventor： Brian S. Hausauer

IPC: G06F1/08 ,  G06F1/04 ,  G06F1/12

CPC classification number: G06F1/08

Abstract: An apparatus is disclosed for smoothly multiplying the frequency of a computer's basic clock during a burst transfer cycle and smoothly resuming the basic clock frequency upon completing the burst transfer cycle. A fixed frequency multiplier is connected to the basic clock to generate a clock whose frequency is a multiple of the basic clock frequency. A decoder which operates synchronously with the fixed frequency multiplier clock responds to control signals of the expansion bus to detect the start and the end of a burst transfer cycle. The decoder also toggles a speed-up signal during the burst transfer cycle on the rising edges of the fixed frequency multiplier clock. The speed-up signal and the basic clock is provided to a variable frequency multiplier which multiplies the frequency of the basic clock when the speed-up signal is toggled and reproduces the frequency of the basic clock when the speed-up signal is deasserted, thus providing a clock signal whose rising edges are aligned with the rising and falling edges of the basic clock and whose frequency is a multiple of the basic clock frequency during the burst transfer cycle.

Abstract translation: 公开了一种用于在突发传送周期期间平滑地乘以计算机基本时钟的频率并且在完成突发传送周期时平滑地恢复基本时钟频率的装置。 固定倍频器连接到基本时钟以产生频率是基本时钟频率的倍数的时钟。 与固定倍频器时钟同步工作的解码器响应于扩展总线的控制信号，以检测突发传送周期的开始和结束。 解码器还在固定倍频器时钟的上升沿期间在突发传送周期期间切换加速信号。 加速信号和基本时钟被提供给可变倍频器，当加速信号被切换时，可变倍频器乘以基本时钟的频率，并且当加速信号被无效时再现基本时钟的频率，因此 提供时钟信号，其上升沿与基本时钟的上升沿和下降沿对齐，并且其频率是脉冲串传送周期期间的基本时钟频率的倍数。

公开(公告)号：USD374858S

公开(公告)日：1996-10-22

申请号：US043132

申请日：1995-08-22

Applicant: Chi-Tsong Chu

Designer： Chi-Tsong Chu

公开(公告)号：US5506997A

公开(公告)日：1996-04-09

申请号：US189078

申请日：1994-01-28

Applicant: David J. Maguire ,  Patrick L. Ferguson

Inventor： David J. Maguire ,  Patrick L. Ferguson

IPC: G06F11/22 ,  G06F13/24 ,  G06F13/40 ,  G06F13/32 ,  G06F13/14 ,  G06F13/30

CPC classification number: G06F11/2284 ,  G06F13/24 ,  G06F13/4027

Abstract: A system for mapping a PCI interrupt signal to any EISA interrupt signal, in which sharing is allowed between PCI interrupts as well as between a PCI interrupt and an EISA interrupt. The actual mapping is performed during the Power On Self Test (POST) procedure, where the computer writes appropriate values into a set of MAP and MASK registers. Each MAP and MASK register corresponds to a PCI interrupt. Thus, by programming the appropriate MAP and MASK register to certain values, the corresponding PCI interrupt can be mapped to the desired EISA interrupt signal. A decode logic then produces a set of final interrupt signals based on the state of the PCI interrupt signals, the MAP and MASK registers, and the EISA interrupt signals. The final interrupt signals are provided to an interrupt controller, which responds to the assertion of the final interrupt signals by asserting an interrupt signal to the microprocessor.

Abstract translation: 用于将PCI中断信号映射到任何EISA中断信号的系统，其中PCI中断之间以及PCI中断和EISA中断之间允许共享。 在开机自检（POST）过程中执行实际映射，其中计算机将适当的值写入一组MAP和MASK寄存器。 每个MAP和MASK寄存器对应于PCI中断。 因此，通过将适当的MAP和MASK寄存器编程为某些值，相应的PCI中断可映射到所需的EISA中断信号。 然后，解码逻辑基于PCI中断信号，MAP和MASK寄存器的状态以及EISA中断信号产生一组最终中断信号。 最后的中断信号被提供给中断控制器，该中断控制器通过向微处理器发出中断信号来响应对最终中断信号的断言。