公开(公告)号：US06898740B2

公开(公告)日：2005-05-24

申请号：US09769953

申请日：2001-01-25

Applicant: Sompong P. Olarig

Inventor： Sompong P. Olarig

IPC: G06F11/20 ,  G06F11/00

CPC classification number: G06F11/2007

Abstract: A core logic chipset for a computer system is provided which can be configured as a bridge between either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus. A common bus having provisions for the PCI and AGP interface signals is connected to the core logic chipset and either an AGP or PCI device(s). The common bus, which is part of a fault-tolerant interconnect system, includes a first bus portion and a lower bus portion. When an error (e.g., a parity error) is detected on the first bus portion, the transaction is transferred over the second bus portion. When an error is detected on the second bus portion, the transaction is transferred over the first bus portion. If errors are detected on both portions, the transaction may be terminated.

Abstract translation: 提供了一种用于计算机系统的核心逻辑芯片组，其可以被配置为加速图形端口（AGP）总线或附加外围部件互连（PCI）总线之间的桥接器。 具有PCI和AGP接口信号的公共总线连接到核心逻辑芯片组以及AGP或PCI设备。 作为容错互连系统的一部分的公共总线包括第一总线部分和下部总线部分。 当在第一总线部分上检测到错误（例如，奇偶校验错误）时，事务通过第二总线部分传送。 当在第二总线部分上检测到错误时，事务通过第一总线部分传送。 如果在两个部分都检测到错误，则可能会终止该事务。

公开(公告)号：US06886109B2

公开(公告)日：2005-04-26

申请号：US09860266

申请日：2001-05-18

Applicant: Sompong P. Olarig ,  Michael F. Angelo ,  Chai S. Heng

Inventor： Sompong P. Olarig ,  Michael F. Angelo ,  Chai S. Heng

IPC: G06F9/445 ,  G06F11/22 ,  G06F11/00

CPC classification number: G06F9/4401 ,  G06F11/2284

Abstract: A computer system includes multiple controllers that assist in executing the Power-On Self Test (POST) sequence to minimize the time required to complete system initialization. By shifting some of the responsibilities for executing the POST sequence to other controllers within the system, the testing and initialization of system devices can proceed concurrently. The controllers interface with peripheral devices, and include a register set that includes command information for initializing the testing and initialization of associated peripherals. The register set also includes dedicated bits for indicating the status of testing and initialization cycles, which can be read by the CPU to determine if testing or initialization is in progress, if it has completed, and if any errors have occurred. The register set also includes a configuration register for indicating configuration information and operating parameters of the initialized drive or peripheral. By distributing the testing and initialization responsibilities to the controllers, execution of the BIOS system software or system initialization software can be expedited, thus minimizing down time caused by initializing the computer system.

Abstract translation: 计算机系统包括多个控制器，它们有助于执行开机自检（POST）顺序，以最小化完成系统初始化所需的时间。 通过将执行POST序列的一些职责转移到系统内的其他控制器，系统设备的测试和初始化可以同时进行。 控制器与外围设备接口，并包括一个寄存器集，其中包含用于初始化相关外设测试和初始化的命令信息。 寄存器集还包括用于指示测试和初始化周期状态的专用位，CPU可以读取它们，以确定测试或初始化是否正在进行，如果已经完成，并且发生任何错误。 寄存器集还包括用于指示初始化的驱动器或外围设备的配置信息和操作参数的配置寄存器。 通过将测试和初始化职责分配给控制器，可以加快执行BIOS系统软件或系统初始化软件，从而最小化由初始化计算机系统造成的停机时间。

公开(公告)号：US06862646B2

公开(公告)日：2005-03-01

申请号：US10034464

申请日：2001-12-28

Applicant: Thomas J. Bonola ,  John E. Larson ,  Sompong P. Olarig

Inventor： Thomas J. Bonola ,  John E. Larson ,  Sompong P. Olarig

IPC: G06F5/10 ,  G06F12/08 ,  G06F13/00

CPC classification number: G06F12/0815 ,  G06F5/10 ,  G06F2212/621

Abstract: The specification discloses a method and related system that allows hardware devices to participate in the coherency domain of a computer system. More particularly, hardware devices such as network interface cards, audio cards, input/output cards, and the like, are allowed to participate on at least a limited basis in the coherency domain by having cache memory that duplicates a FIFO buffer in main memory used to exchange information between software and the hardware. To exchange information, software writes to the FIFO buffer which invalidates the data in the cache-type memory of the hardware device, and the invalidation message acts to notify the hardware device of the availability of information in the FIFO buffer.

Abstract translation: 本说明书公开了允许硬件设备参与计算机系统的相干域的方法和相关系统。 更具体地，通过使用在主存储器中复制FIFO缓冲器的高速缓存存储器，允许在至少有限的基础上参与相干域中的诸如网络接口卡，音频卡，输入/输出卡等的硬件设备 在软件和硬件之间交换信息。 为了交换信息，软件向FIFO缓冲器写入，使硬件设备的高速缓存型存储器中的数据无效，并且无效消息用于向硬件设备通知FIFO缓冲器中的信息的可用性。

公开(公告)号：US06609204B1

公开(公告)日：2003-08-19

申请号：US09280314

申请日：1999-03-29

Applicant: Sompong P. Olarig ,  Michael F. Angelo ,  Chi Kim Sides

Inventor： Sompong P. Olarig ,  Michael F. Angelo ,  Chi Kim Sides

IPC: H04L900

CPC classification number: H04B3/542 ,  H04B2203/5408 ,  H04B2203/5445 ,  H04B2203/5458

Abstract: A computer system and method in which an electrically controlled “hoodlock,” which prevents the computer's chassis from unauthorized opening, can be remotely accessed through powerline communications.

Abstract translation: 可以通过电力线通信来远程访问防止计算机机箱未经授权打开的电控“遮罩”的计算机系统和方法。

公开(公告)号：US06587909B1

公开(公告)日：2003-07-01

申请号：US09519138

申请日：2000-03-06

Applicant: Sompong P. Olarig ,  Chi Kim Sides ,  Thomas J. Bonola

Inventor： Sompong P. Olarig ,  Chi Kim Sides ,  Thomas J. Bonola

IPC: G06F1300

CPC classification number: G06F13/4081

Abstract: A computer-system includes a memory bus, a connector and a controller. The connector is configured to receive a memory module and prevent removal of the memory module from the connector in a first state. The connector allows removal of the memory module from the connector in a second state. The controller is configured to change a connection status between the connector and the memory bus in response to the connector changing from one of the states to the other state. A central processing unit of the computer system is configured to use the memory bus to store data in the memory module.

Abstract translation: 计算机系统包括存储器总线，连接器和控制器。 连接器被配置为接收存储器模块并且在第一状态下防止从连接器移除存储器模块。 该连接器允许在第二状态下从连接器移除存储器模块。 控制器被配置为响应于连接器从状态之一改变到另一状态来改变连接器和存储器总线之间的连接状态。 计算机系统的中央处理单元被配置为使用存储器总线将数据存储在存储器模块中。

公开(公告)号：US06370657B1

公开(公告)日：2002-04-09

申请号：US09196264

申请日：1998-11-19

Applicant: Kenneth A. Jansen ,  Sompong P. Olarig ,  John E. Jenne

Inventor： Kenneth A. Jansen ,  Sompong P. Olarig ,  John E. Jenne

IPC: G06F1100

CPC classification number: G06F11/0793 ,  G06F11/0724 ,  G06F13/4081

Abstract: A scheme may be used to remove or replace a processor in a multiprocessor computer without the need for turning the computer off to replace the processor. In this scheme, the bus to which the processor is coupled is identified so that all processors coupled to the bus may be placed in sleep mode. This act does not alter the normal operation of processors that may be coupled to another bus. Once the processors are in sleep mode, the processor may be removed or replaced. Afterward, all processors may be returned to normal operation.

Abstract translation: 可以使用方案来移除或替换多处理器计算机中的处理器，而不需要关闭计算机来替换处理器。 在该方案中，识别处理器耦合到的总线，使得耦合到总线的所有处理器可以被置于睡眠模式。 该动作不会改变可能耦合到另一总线的处理器的正常操作。 一旦处理器处于睡眠模式，处理器可能会被删除或更换。 之后，所有处理器都可以恢复正常运行。

公开(公告)号：US06363449B1

公开(公告)日：2002-03-26

申请号：US09280313

申请日：1999-03-29

Applicant: Chi Kim Sides ,  Michael F. Angelo ,  Sompong P. Olarig

Inventor： Chi Kim Sides ,  Michael F. Angelo ,  Sompong P. Olarig

IPC: G06F1300

CPC classification number: H04B3/546 ,  H04B3/548 ,  H04B2203/5445 ,  H04B2203/5458

Abstract: A method and system of interchassis and intrachassis computer component command and control. The existing power rail is used for network connectivity for intrachassis command and control. An existing common power mains can be used for interchassis command and control. Further, a protocol, for example, the Consumer Electronic Bus (CEBus) protocol (or a CEBus protocol modified for the particular power rail) can be used to provide interchassis and intrachassis platform management functionality. This management functionality is similar to that provided by the proposed Intelligent Platform Management Interface (IPMI) specification. A chassis bridge controller is used to interface the intrachassis power rail command and control infrastructure to an exterior network. External systems (interchassis communications) can communicate to the bridge via the particular protocol over an existing common power mains as a secondary channel exterior network. However, the management functionality is implemented intrachassis, that is, it is applied to the internal components of the machine.

Abstract translation: 一种机架和机载计算机组件命令和控制的方法和系统。 现有的电力轨道用于网络连接，用于intrachassis命令和控制。 现有的公共电源可用于机架间的指令和控制。 此外，可以使用诸如消费电子总线（CEBus）协议（或针对特定电力轨道修改的CEBus协议）的协议来提供机架间和平台内平台管理功能。 该管理功能类似于所提出的智能平台管理界面（IPMI）规范。 机箱桥控制器用于将机载电源指挥和控制基础设施连接到外部网络。 外部系统（机架间通信）可以通过特定协议通过现有公共电源作为辅助信道外部网络与桥接器进行通信。 但是，管理功能是在内部实现的，也就是应用于机器的内部组件。

公开(公告)号：US5867444A

公开(公告)日：1999-02-02

申请号：US937535

申请日：1997-09-25

Applicant: Hung Q. Le ,  Sompong P. Olarig

Inventor： Hung Q. Le ,  Sompong P. Olarig

IPC: G11C8/00

CPC classification number: G11C7/1045 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/10 ,  G11C2207/105

Abstract: A programmable memory device including a register that stores a programmable mode select bit, a data input, a control input and decode circuitry that decodes the mode select bit to determine whether the memory device operates in either a check mode or a mask mode. The control input receives at least one control bit for each data byte received by the memory device during a write operation or cycle. The function of the control bit(s) depends upon the mode select bit. In a check mode of operation, each control bit functions as a parity/check bit for a corresponding data byte, where the memory device stores the check bit with its corresponding data byte during each write cycle. In the mask mode of operation, each control bit functions as a mask bit for a corresponding data byte, where the memory device selectively stores or masks the data byte depending upon the state of the corresponding mask bit.

Abstract translation: 一种可编程存储器件，包括存储可编程模式选择位的寄存器，数据输入，解码模式选择位的控制输入和解码电路，以确定存储器件是否以检查模式或掩模模式工作。 在写入操作或周期期间，控制输入接收由存储器件接收的每个数据字节的至少一个控制位。 控制位的功能取决于模式选择位。 在检查操作模式中，每个控制位用作相应数据字节的奇偶校验位，其中存储器件在每个写入周期期间将检查位与其对应的数据字节存储。 在掩模操作模式中，每个控制位用作相应数据字节的掩码位，存储器件根据对应的掩码位的状态有选择地存储或屏蔽数据字节。

公开(公告)号：US5859911A

公开(公告)日：1999-01-12

申请号：US840795

申请日：1997-04-16

Applicant: Michael F. Angelo ,  Sompong P. Olarig ,  George D. Wisecup

Inventor： Michael F. Angelo ,  Sompong P. Olarig ,  George D. Wisecup

IPC: G06F12/14 ,  G06F21/00 ,  H04K1/00

CPC classification number: G06F21/572 ,  G06F12/1408 ,  G06F2211/1097

Abstract: In a computer system having a receiving computer and a source computer, a method for the remote flashing of the BIOS in the receiving computer including the steps of transferring the flash information from the source computer to the receiving computer, with the flash information including the flash code, the flash code instructions and an encrypted digital signature corresponding to the flash code. The receiving computer is operably placed in a secure mode. A hash value corresponding to the flash information is calculated, and the hash value from the flash information is decrypted. The flash code is validated by comparing the decrypted hash value of the flash information to the calculated hash value, and if validated, the BIOS if flashed with the new flash code.

Abstract translation: 在具有接收计算机和源计算机的计算机系统中，用于在接收计算机中远程闪烁BIOS的方法包括以下步骤：将闪存信息从源计算机传送到接收计算机，闪存信息包括闪存 代码，闪存代码指令和对应于闪存代码的加密数字签名。 接收计算机可操作地置于安全模式。 计算与闪光信息对应的散列值，对来自闪光灯信息的哈希值进行解密。 闪存代码通过将闪存信息的解密散列值与计算出的散列值进行比较来验证，如果验证，则BIOS将使用新的闪存代码闪烁。

公开(公告)号：US5835948A

公开(公告)日：1998-11-10

申请号：US324016

申请日：1994-10-14

Applicant: Sompong P. Olarig ,  Jens K. Ramsey ,  Michael J. Collins

Inventor： Sompong P. Olarig ,  Jens K. Ramsey ,  Michael J. Collins

IPC: G06F12/08

CPC classification number: G06F12/0879 ,  G06F12/0859

Abstract: In a microcomputer system implementing cache memory, a multiple-way cache is implemented in a single-bank memory. Instead of using chip output enables on a separate physical chip for each way of the multiple-way cache, an address line of a single bank of memory is used to select between ways. In this way, fewer parts can be used, and a single-bank memory can be used for a multiple-way cache.

Abstract translation: 在实现高速缓冲存储器的微计算机系统中，在单行存储器中实现多路高速缓存。 代替使用芯片输出，可以在多路缓存的每种方式的单独物理芯片上实现，单个存储器的地址线用于在各种方式之间进行选择。 以这种方式，可以使用更少的部件，并且单行存储器可以用于多路缓存。