公开(公告)号：US20220392998A1

公开(公告)日：2022-12-08

申请号：US17388263

申请日：2021-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

Abstract: A semiconductor device includes nanosheets between the source/drain regions, and a gate structure over the substrate and between the source/drain regions, the gate structure including a gate dielectric material around each of the nanosheets, a work function material around the gate dielectric material, a first capping material around the work function material, a second capping material around the first capping material, wherein the second capping material is thicker at a first location between the nanosheets than at a second location along a sidewall of the nanosheets, and a gate fill material over the second capping material.

公开(公告)号：US20220392889A1

公开(公告)日：2022-12-08

申请号：US17647046

申请日：2022-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L29/66

Abstract: A semiconductor device includes a first device over a substrate, wherein the first device includes a gate stack including a gate electrode material; a source/drain region in the substrate adjacent the gate stack; a first isolation region surrounding the gate stack; a gate contact over and contacting the gate stack, wherein the gate contact includes a gate contact material; and a second isolation region surrounding the gate contact; and a second device over the substrate, wherein the second device includes a first parallel capacitor including first electrodes, wherein the first electrodes include the gate electrode material, wherein the first isolation region separates the first electrodes; and a second parallel capacitor over the first parallel capacitor, wherein the second parallel capacitor includes second electrodes connected to the first electrodes, wherein the second electrodes include the gate contact material, wherein adjacent second electrodes are separated by the second isolation region.

公开(公告)号：US20220384484A1

公开(公告)日：2022-12-01

申请号：US17884348

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chih-Yu Chang ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L27/11597 ,  H01L29/06 ,  H01L27/11587

Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

公开(公告)号：US20220384249A1

公开(公告)日：2022-12-01

申请号：US17818390

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Tai-Chun Huang ,  Chih-Tang Peng ,  Chi On Chui

IPC: H01L21/762 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/764

Abstract: A semiconductor device a method of forming the same are provided. The semiconductor device includes a substrate, a first isolation structure and a second isolation structure over the substrate, a semiconductor fin over the substrate and between the first isolation structure and the second isolation structure, and a third isolation structure extending through the semiconductor fin and between the first isolation structure and the second isolation structure. A top surface of the semiconductor fin is above a top surface of the first isolation structure and a top surface of the second isolation structure. The third isolation structure includes a first dielectric material and a second dielectric material over the first dielectric material. An interface between the first dielectric material and the second dielectric material is below the top surface of the first isolation structure and the top surface of the second isolation structure.

公开(公告)号：US11508826B2

公开(公告)日：2022-11-22

申请号：US16952503

申请日：2020-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/78

Abstract: A method includes forming a gate dielectric layer on a semiconductor region, and depositing a first aluminum-containing work function layer using a first aluminum-containing precursor. The first aluminum-containing work function layer is over the gate dielectric layer. A second aluminum-containing work function layer is deposited using a second aluminum-containing precursor, which is different from the first aluminum-containing precursor. The second aluminum-containing work function layer is deposited over the first aluminum-containing work function layer. A conductive region is formed over the second aluminum-containing work function layer.

公开(公告)号：US11502081B2

公开(公告)日：2022-11-15

申请号：US17182733

申请日：2021-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/033 ,  H01L29/66 ,  H01L21/02

Abstract: In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a n-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a p-type work function metal, the p-type work function metal different from the n-type work function metal; and a fill layer on the second work function tuning layer.

公开(公告)号：US11501812B2

公开(公告)日：2022-11-15

申请号：US17099094

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Jacob Wang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L29/78 ,  G11C11/22 ,  H01L29/51

Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.

公开(公告)号：US20220359655A1

公开(公告)日：2022-11-10

申请号：US17869414

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.

公开(公告)号：US20220358983A1

公开(公告)日：2022-11-10

申请号：US17814755

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Wang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: G11C11/22 ,  H01L29/78 ,  H01L29/51

Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.

公开(公告)号：US20220336584A1

公开(公告)日：2022-10-20

申请号：US17341034

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions, the gate structure including: a gate dielectric material around each of the nanosheets; a work function material around the gate dielectric material; a liner material around the work function material, where the liner material has a non-uniform thickness and is thicker at a first location between the nanosheets than at a second location along sidewalls of the nanosheets; and a gate electrode material around at least portions of the liner material.