Doppler shift correction sub-system for communication device

    公开(公告)号:US10419100B2

    公开(公告)日:2019-09-17

    申请号:US14399581

    申请日:2012-05-07

    IPC分类号: H04B7/155 H04L27/10 H04W64/00

    摘要: Certain aspects and embodiments are directed to a Doppler shift correction sub-system that can be disposed in a mobile repeater. The Doppler shift correction sub-system can include a processor and a frequency-shifting module. The processor can be configured to determine a corrective frequency shift based on a velocity of the repeater relative to a source and a representative transmission frequency. The processor can provide the corrective frequency shift to a frequency-shifting module. The frequency-shifting module can be configured to shift the signal using the corrective frequency shift prior to transmitting the signal to a destination, such as a mobile device.

    Radar hardware accelerator
    34.
    发明授权

    公开(公告)号:US10330773B2

    公开(公告)日:2019-06-25

    申请号:US15184715

    申请日:2016-06-16

    摘要: A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.