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公开(公告)号：US11231484B2
公开(公告)日：2022-01-25
申请号：US16816588
申请日：2020-03-12
发明人： Karthik Subburaj , Brian Paul Ginsburg , Daniel Colum Breen , Sandeep Rao , Karthik Ramasubramanian
IPC分类号： G01S7/40 , G01S7/03 , G01S7/35 , G01S13/931 , G01S13/02
摘要： Methods for monitoring of performance parameters of one or more receive channels and/or one or more transmit channels of a radar system-on-a-chip (SOC) are provided. The radar SOC may include a loopback path coupling at least one transmit channel to at least one receive channel to provide a test signal from the at least one transmit channel to the at least one receive channel when the radar SOC is operated in test mode. In some embodiments, the loopback path includes a combiner coupled to each of one or more transmit channels, a splitter coupled to each of one or more receive channels, and a single wire coupling an output of the combiner to an input of the splitter.
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公开(公告)号：US11194017B2
公开(公告)日：2021-12-07
申请号：US16984262
申请日：2020-08-04
摘要： A FMCW radar system with a built-in self-test (BIST) system for monitoring includes a receiver, a transmitter, and a frequency synthesizer. A FMCW chirp timing engine controls timing of operations at least one radar component. The BIST system includes at least one switchable coupling for coupling a first plurality of different analog signals including from a first plurality of selected nodes in the receiver or transmitter that are all coupled to a second number of monitor analog-to-digital converters (ADCs). The second number is less than (
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公开(公告)号：US11023323B2
公开(公告)日：2021-06-01
申请号：US16788004
申请日：2020-02-11
摘要： Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.
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公开(公告)号：US10782389B2
公开(公告)日：2020-09-22
申请号：US15676547
申请日：2017-08-14
IPC分类号： G01S7/03 , G01S13/34 , G01S13/931 , H01Q1/32
摘要： A device includes a circuit board having thereon, a controlling component, a first radar chip and a second radar chip. The first radar chip includes a first radar transmission antenna, a second radar transmission antenna and a first radar receiver antenna array. The second radar chip includes a second radar receiver antenna array. The controlling component can control the first radar chip and the second radar chip. The first radar transmission antenna can transmit a first radar transmission signal. The second radar transmission antenna can transmit a second radar transmission signal. The second radar chip is spaced from the first radar chip so as to create a virtual receiver antenna array between the first radar receiver antenna array and the second radar receiver antenna array.
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公开(公告)号：US20180372840A1
公开(公告)日：2018-12-27
申请号：US16107000
申请日：2018-08-21
摘要： The disclosure provides a radar apparatus. The radar apparatus includes a transmitter that transmits a first chirp. The first chirp is scattered by one or more obstacles to generate a first plurality of scattered signals. A plurality of receivers receives the first plurality of scattered signals. Each receiver of the plurality of receivers generates a digital signal in response to a scattered signal of the first plurality of scattered signals. A processor is coupled to the plurality of receivers and receives the digital signals from the plurality of receivers. The processor performs range FFT (fast fourier transform) and angle FFT on the digital signals received from the plurality of receivers to generate a first matrix of complex samples.
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公开(公告)号：US20170363714A1
公开(公告)日：2017-12-21
申请号：US15676547
申请日：2017-08-14
CPC分类号： G01S7/032 , G01S13/343 , G01S13/931 , H01Q1/3233
摘要： A device includes a circuit board having thereon, a controlling component, a first radar chip and a second radar chip. The first radar chip includes a first radar transmission antenna, a second radar transmission antenna and a first radar receiver antenna array. The second radar chip includes a second radar receiver antenna array. The controlling component can control the first radar chip and the second radar chip. The first radar transmission antenna can transmit a first radar transmission signal. The second radar transmission antenna can transmit a second radar transmission signal. The second radar chip is spaced from the first radar chip so as to create a virtual receiver antenna array between the first radar receiver antenna array and the second radar receiver antenna array.
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公开(公告)号：US20170315211A1
公开(公告)日：2017-11-02
申请号：US15642880
申请日：2017-07-06
摘要： The disclosure provides a radar apparatus for estimating a position and a velocity of a plurality of obstacles. The radar apparatus includes a slave radar chip. A master radar chip is coupled to the slave radar chip. The master radar chip includes a local oscillator that generates a transmit signal. The slave radar chip receives the transmit signal on a first path and sends the transmit signal back to the master radar chip on a second path. A delay detect circuit is coupled to the local oscillator and receives the transmit signal from the slave radar chip on the second path and the transmit signal from the local oscillator. The delay detect circuit estimates a routing delay from the transmit signal received from the slave radar chip on the second path and from the transmit signal received from the local oscillator.
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公开(公告)号：US20170212214A1
公开(公告)日：2017-07-27
申请号：US15004443
申请日：2016-01-22
IPC分类号： G01S7/35
CPC分类号： G01S7/352 , G01S7/4021 , G01S13/931 , G01S2007/358 , G01S2007/406
摘要： A radar system is provided that includes a receive channel configured to receive a reflected signal and to generate a first digital intermediate frequency (IF) signal based on the reflected signal, a reference receive channel configured to receive a reflected signal and to generate a second digital IF signal based on the reflected signal, and digital mismatch compensation circuitry coupled to receive the first digital IF signal and the second digital IF signal, the digital mismatch compensation circuitry configured to process the first digital IF signal and the second digital IF signal to compensate for mismatches between the receive channel and the reference receive channel.
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公开(公告)号：US20150015438A1
公开(公告)日：2015-01-15
申请号：US14037052
申请日：2013-09-25
IPC分类号： G01S19/24
CPC分类号： G01S19/24 , G01S19/246 , G01S19/25
摘要： A method of acquiring a satellite signal in a GNSS receiver includes multiplying a received signal with a hypothesized doppler frequency signal to generate a frequency shifted signal. A PN code sequence signal is multiplied with the frequency shifted signal to generate a PN wiped signal. A windowing function signal is multiplied with the PN wiped signal to generate a windowed signal. The windowed signal is integrated coherently for a first predefined time to generate a coherent accumulated data.
摘要翻译： 在GNSS接收机中获取卫星信号的方法包括将接收信号与假设的多普勒频率信号相乘以产生频移信号。 PN码序列信号与频移信号相乘以产生PN擦除信号。 加窗功能信号与PN擦除信号相乘以产生加窗信号。 窗口信号被相干地整合在第一预定义时间以产生相干累积数据。
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公开(公告)号：US08897401B2
公开(公告)日：2014-11-25
申请号：US14309303
申请日：2014-06-19
CPC分类号： H03G3/3036 , H03M1/185 , H04B1/1036 , H04B17/309 , H04B17/345 , H04L27/08
摘要： Automatic gain control in a receiver. A method for controlling operating range of an analog-to-digital converter (ADC) by an automatic gain control circuit includes estimating a peak-to-average ratio corresponding to an analog signal from digital samples of the analog signal. The method includes determining a peak value corresponding to the analog signal based on the peak-to-average ratio. Further, the method includes maintaining magnitude of the analog signal at an input of the ADC and gain of the receiver based on the peak value.
摘要翻译： 接收机自动增益控制。 用于通过自动增益控制电路控制模数转换器（ADC）的操作范围的方法包括从模拟信号的数字样本估计对应于模拟信号的峰均比。 该方法包括基于峰均比来确定与模拟信号相对应的峰值。 此外，该方法包括基于峰值来维持ADC的输入处的模拟信号的幅度和接收机的增益。
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