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公开(公告)号：US10986767B2
公开(公告)日：2021-04-27
申请号：US16938821
申请日：2020-07-24
申请人： AgJunction LLC
摘要： Some embodiments may include a control system configured to monitor an online queue associated with a remote server for the presence of updated control software content; in the case of the presence of updated control software content in the online queue, provide data based thereon in an offline queue, wherein a portable computing device includes a storage for the offline queue; waiting for a time period in which a wired communication interface of the portable computing device is attached to a wired interface of the vehicle or a wireless communication interface of the vehicle is in range of a wireless communication interface of the portable computing device; and in the time period, transferring contents of the offline queue to the vehicle, wherein a processor of the vehicle distributes update(s) included in the contents to one or more of the GNSS receiver, the actuator assembly, and the steering control module.
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公开(公告)号：US10979214B2
公开(公告)日：2021-04-13
申请号：US16520996
申请日：2019-07-24
申请人： Martin Spence Denham
发明人： Martin Spence Denham
摘要： A Secure Hash Algorithm 256 (SHA-256) expander operates over multiple cycles to convert 16 message words, M(t), into 64 working values, W(t), for input into a SHA-256 compressor. As the expander operates to produce W(t), it computes partial values of W(t) as soon as the necessary data operands are available in cycle time. Once computed, the partial values are retained and shifted and any unneeded original shift source values are discarded. When the shift register outputs finally arrive at the output, W(t) is already computed. The expander allows for one-write-port, one-read-port register files to be used in some integrated circuit embodiments. The expander also leads to improvements in adder delays, energy consumption, and area consumption when implemented as an integrated circuit.
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公开(公告)号：US10949366B2
公开(公告)日：2021-03-16
申请号：US16735644
申请日：2020-01-06
摘要： Provided are a computer program product, system, and method for using at least one machine learning module to select a priority queue from which to process an Input/Output (I/O) request. Input I/O statistics are provided on processing of I/O requests at the queues to at least one machine learning module. Output is received from the at least one machine learning module for each of the queues. The output for each queue indicates a likelihood that selection of an I/O request from the queue will maintain desired response time ratios between the queues. The received output for each of the queues is used to select a queue of the queues. An I/O request from the selected queue is processed.
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公开(公告)号：US20210072928A1
公开(公告)日：2021-03-11
申请号：US17092248
申请日：2020-11-07
申请人： Tyson York Winarski
发明人： Tyson York Winarski
IPC分类号： G06F3/06 , G06F5/06 , G06F12/122 , H04L9/06
摘要： An archival blockchain system is disclosed that includes a cache-tier storage level where data is stored before it has met a first aging criteria, a disk-tier storage level where the data is migrated to and stored within archival blockchain blocks after it has met the first aging criteria. When the archival blockchain blocks containing the data meet a second aging criteria they are migrated to a tape-tier storage level where the disk-tier archival blockchain blocks are stored within another archival blockchain block stored on the tape-tier. This archival blockchain system also includes a blockchain appliance in digital data communication with the cache-tier, disk-tier, and tape-tier storage levels that maintains a ledger that stores data pointers to the data stored on the cache-tier, disk-tier, and tape-tier storage levels to logically link them into a contiguous data set.
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公开(公告)号：US20210034424A1
公开(公告)日：2021-02-04
申请号：US16940217
申请日：2020-07-27
发明人： Nathan Chrisman
摘要： A system and corresponding method employ an object-oriented memory device. The object-oriented memory device includes at least one physical memory and a hardware controller. The hardware controller is coupled intra the object-oriented memory device to the at least one physical memory. The hardware controller (i) decodes an object-oriented message received from a hardware client of the object-oriented memory device and (ii) performs an action for the hardware client based on the object-oriented message received and decoded. The object-oriented message is associated with an object instantiated or to-be-instantiated in the at least one physical memory. The action is associated with the object. The object-oriented memory device alleviates the hardware client(s) from having to manage structure of respective data stored in the at least one physical memory, obviating duplication of code among the hardware clients for managing same and efforts for design and verification thereof.
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公开(公告)号：US20210034380A1
公开(公告)日：2021-02-04
申请号：US16940229
申请日：2020-07-27
发明人： Nathan Chrisman
摘要： A hardware client and corresponding method employ an object-oriented memory device. The hardware client generates an object-oriented message associated with an object of an object class. The object class includes at least one data member and at least one method. The hardware client transmits the object-oriented message generated to the object-oriented memory device via a hardware communications interface. The hardware communications interface couples the hardware client to the object-oriented memory device. The object is instantiated or to-be instantiated in at least one physical memory of the object-oriented memory device according to the object class. The at least one method enables the object-oriented memory device to access the at least one data member for the hardware client.
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公开(公告)号：US10896119B1
公开(公告)日：2021-01-19
申请号：US16180811
申请日：2018-11-05
申请人： Xilinx, Inc.
发明人： Ahmad R. Ansari , Felix Burton , Henry C. Yu
摘要： An input-output circuit is coupled to a plurality of serial communication paths and to a physical point-to-point interface. The input-output circuit is configured to transmit data received on the plurality of serial communication paths over the physical point-to-point interface. An application circuit is coupled to the input-output circuit and is configured to communicate via a first one of the paths in performing application functions. A bridge circuit is coupled to the input-output circuit and is configured to communicate via a second one of the paths. A debug circuit is coupled to the application circuit and to the bridge circuit. The debug circuit is configured to capture debug data of the application circuit and provide the debug data to the bridge circuit for communication via the second one of the paths.
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公开(公告)号：US10891185B2
公开(公告)日：2021-01-12
申请号：US15314831
申请日：2014-08-08
IPC分类号： G11C29/06 , G06F11/10 , G11C29/44 , G11C29/50 , G11C29/12 , G06F5/06 , G06F11/07 , G11C11/41
摘要： Example implementations relate to tracking memory unit errors on a memory device. In example implementations, a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value.
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公开(公告)号：US10884964B2
公开(公告)日：2021-01-05
申请号：US16436771
申请日：2019-06-10
申请人： Altera Corporation
发明人： Huy Ngo , Keith Duwel , David W. Mendel
摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.
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公开(公告)号：US20200371762A1
公开(公告)日：2020-11-26
申请号：US16983429
申请日：2020-08-03
发明人： Kai CHIRCA , Timothy D. ANDERSON , Todd T. HAHN , Alan L. DAVIS
摘要： A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.
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