公开(公告)号：US5646051A

公开(公告)日：1997-07-08

申请号：US435254

申请日：1995-05-05

Applicant: Stuart A. Solin

Inventor： Stuart A. Solin

IPC: G11B5/012 ,  G11B5/39 ,  H01L43/08 ,  H01L43/12 ,  H01L21/00

CPC classification number: H01L43/12 ,  G11B5/3993 ,  G11B5/012 ,  Y10S148/136

Abstract: A magnetic sensor for use in a reading head for a magnetic disk is formed by depositing a plurality of planar superimposed layers of metals and semiconductors and using for the active element a planar structure formed orthogonal to the superimposed layers by their edges. Specifically, the edges of the superimposed layer form on the orthogonal planar surface a Corbino-disk structure in which conductive regions form inner and outer electrodes about an annular semiconductive region with high magnetoresistance, such as is provided by cadmium mercury telluride or indium antimonide.

Abstract translation: 用于磁盘读取头的磁传感器是通过沉积多个金属和半导体的平面叠加层而形成的，并且通过它们的边缘将与叠加层正交的平面结构用于有源元件。 具体地说，重叠层的边缘在正交平面上形成Corbino-disc结构，其中导电区域围绕例如由碲化镉汞或锑化铟提供的具有高磁阻的环形半导体区域形成内电极和外电极。

公开(公告)号：US5489547A

公开(公告)日：1996-02-06

申请号：US247443

申请日：1994-05-23

Applicant: John P. Erdeljac ,  Louis N. Hutter

Inventor： John P. Erdeljac ,  Louis N. Hutter

IPC: H01L21/02 ,  H01L21/3215 ,  H01L27/06 ,  H01L21/70

CPC classification number: H01L28/20 ,  H01L21/32155 ,  H01L27/0688 ,  Y10S148/136 ,  Y10S148/146 ,  Y10S257/904 ,  Y10S438/934

Abstract: A semiconductor device having a p type polysilicon resistor (56) with a moderate sheet resistance and low temperature coefficient of resistance is formed by a double-level polysilicon process. The process also produces n and p-channel transistors (44, 50), a capacitor having upper and lower n type polysilicon capacitor plates (36, 26), an n type polysilicon resistor (32) having a high sheet resistance, and an n type resistor (34) having a low sheet resistance. The p type doping used to form the source/drain regions (48) of p-channel transistor (50) counterdopes n type second level polysilicon to form p type polysilicon resistor (56) without effecting capacitor plates (36, 26) or the n type resistors (32, 34).

Abstract translation: 具有中等薄层电阻和低电阻温度系数的p型多晶硅电阻器（56）的半导体器件通过双级多晶硅工艺形成。 该工艺还产生n沟道晶体管和p沟道晶体管（44,50），具有上和下n型多晶硅电容器板（36,26）的电容器，具有高薄层电阻的n型多晶硅电阻器（32）和n 型电阻器（34）。 用于形成p沟道晶体管（50）的源极/漏极区域（48）的p型掺杂反向型n型第二级多晶硅以形成p型多晶硅电阻器（56）而不影响电容器板（36,26）或n 型电阻器（32,34）。

公开(公告)号：US5446295A

公开(公告)日：1995-08-29

申请号：US110608

申请日：1993-08-23

Applicant: David Whitney

Inventor： David Whitney

IPC: H01L31/111 ,  H01L29/74

CPC classification number: H01L31/1113 ,  Y10S148/136

Abstract: An optically triggered silicon controlled rectifier (SCR) circuit (20) has a number of semiconductor layers diffused into an N- substrate (21). The layers form an SCR (50) having a P+ anode region (25), a P+ gate region (24), and an N+ cathode region (27). An adjustable base-shunt resistance, in the form of a P- channel depletion mode MOSFET (Q3), connects between the SCR gate region and the cathode region. The MOSFET includes a MOSFET gate region (35), a P+ drain region (24), a P-- channel (26), and a P+ source region (23). The substrate also accommodates a PN photodiode (22, D1) which connects to the MOSFET gate region for switching the MOSFET on and off in response to incident optical radiation (L) thereon. The SCR gate region also comprises photosensitive material. When sufficient optical radiation illuminates the photodiode and the SCR gate region, the MOSFET is turned off and the SCR is triggered, permitting anode-to-cathode current to flow. When insufficient optical radiation is present, the MOSFET is turned on and provides a low-resistance shunt path which prevents the SCR gate region from triggering the SCR.

Abstract translation: 光触发可控硅整流器（SCR）电路（20）具有扩散到N基板（21）中的多个半导体层。 这些层形成具有P +阳极区域（25），P +栅极区域（24）和N +阴极区域（27）的SCR（50）。 以P沟道耗尽型MOSFET（Q3）的形式的可调节分路电阻连接在SCR栅极区域和阴极区域之间。 MOSFET包括MOSFET栅极区域（35），P +漏极区域（24），P沟道（26）和P +源极区域（23）。 衬底还容纳连接到MOSFET栅极区域的PN光电二极管（22，D1），用于响应于其上的入射光辐射（L）而开启和关闭MOSFET。 SCR栅极区域还包括感光材料。 当足够的光辐射照射光电二极管和SCR栅极区域时，MOSFET被关断，SCR被触发，允许阳极到阴极的电流流动。 当存在不足的光辐射时，MOSFET导通，并提供低阻分流路径，防止SCR栅极区域触发SCR。

公开(公告)号：US5420053A

公开(公告)日：1995-05-30

申请号：US237995

申请日：1994-05-04

Applicant: Shinichi Miyazaki

Inventor： Shinichi Miyazaki

IPC: H01L27/04 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L21/265

CPC classification number: H01L21/8221 ,  H01L27/0688 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/136

Abstract: A collector region is formed in a semiconductor substrate. An insulating layer is formed on the semiconductor substrate, and a non-monocrystalline silicon layer is deposited thereon. The non-monocrystalline silicon layer is annealed to obtain a polycrystalline silicon layer which is patterned into a polycrystalline silicon resistor. The polycrystalline silicon resistor is covered by an insulating layer. Thereafter, a base region is formed, and an emitter region is formed in the base region.

Abstract translation: 在半导体衬底中形成集电极区域。 在半导体衬底上形成绝缘层，在其上沉积非单晶硅层。 对非单晶硅层进行退火以获得图案化为多晶硅电阻器的多晶硅层。 多晶硅电阻被绝缘层覆盖。 此后，形成基极区域，并且在基极区域中形成发射极区域。

公开(公告)号：US5356825A

公开(公告)日：1994-10-18

申请号：US752592

申请日：1991-09-26

Applicant: Hiroki Hozumi ,  Shinichi Araki

Inventor： Hiroki Hozumi ,  Shinichi Araki

IPC: H01L27/04 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L21/70

CPC classification number: H01L27/0688 ,  Y10S148/136 ,  Y10S438/909

Abstract: A resistor (45) of semiconductor material is formed on an insulating layer (42), then a silicon nitride film (46) is deposited on the entire surface including the resistor (45), and a silicon dioxide film (47) is sequentially deposited thereon, and thereafter electrodes (49A) and (49B)of the resistor (45) are formed, thereby preventing the fragility of the insulating layer (51) at step portions of the resistor (45), preventing the breakage of the electrodes and interconnections, and improving a withstand voltage between the resistor (45) and the interconnections crossing over it to thereby improve yield of a semiconductor device. An impurity (64) is introduced into a semiconductor film (63) to be a resistor by the ion implantation technique to thereby change the state of the film into an amorphous state, semiconductor film (63a) is heated in atmosphere including hydrogen compound gas and/or hydrogen gas, and then heated to activate it to thereby form a resistor (67), so that a resistance value of the resistor (67) at a region where the impurity is highly dosed can be decreased progressively.

Abstract translation: PCT No.PCT / JP90 / 01698 Sec。 371日期1991年9月26日 102（e）1991年9月26日PCT PCT 1990年12月26日PCT公布。 出版物WO91 / 10262 日期：1991年7月11日。在绝缘层（42）上形成半导体材料的电阻器（45），然后在包括电阻器（45）的整个表面上沉积氮化硅膜（46），并且将二氧化硅 薄膜（47）依次沉积在其上，然后形成电阻器（45）的电极（49A）和（49B），从而防止在电阻器（45）的台阶处绝缘层（51）的脆弱性，从而防止 电极和互连的断裂，以及改善电阻器（45）和与其交叉的互连之间的耐受电压，从而提高半导体器件的产量。 通过离子注入技术将杂质（64）引入到半导体膜（63）中作为电阻器，从而将膜的状态改变为非晶态，半导体膜（63a）在包含氢化合物气体的气氛中被加热， /或氢气，然后加热以使其激活，从而形成电阻器（67），使得电阻器（67）在杂质浓度高的区域的电阻值可以逐渐降低。

公开(公告)号：US5316964A

公开(公告)日：1994-05-31

申请号：US988342

申请日：1992-12-08

Applicant: William H. Gross

Inventor： William H. Gross

IPC: H01L21/329 ,  H01L21/761 ,  H01L21/70

CPC classification number: H01L29/66166 ,  H01L21/761 ,  Y10S148/136

Abstract: An integrated circuit having diffused resistors formed in a low impurity concentration isolation region.

Abstract translation: 具有形成在低杂质浓度隔离区域的扩散电阻器的集成电路。

公开(公告)号：US5132237A

公开(公告)日：1992-07-21

申请号：US647494

申请日：1991-01-28

Applicant: James A. Matthews

Inventor： James A. Matthews

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417

CPC classification number: H01L21/28211 ,  H01L21/28525 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/136

Abstract: A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members which are electrically isolated from the first polysilicon members. Impurities are diffused from the polysilicon members into the substrate to form the source/drain regions of the MOS transistors, and the extrinsic base and emitter regions of the NPN transistors. The final processing steps include those required for the interconnection of the MOS and NPN transistors.

公开(公告)号：US4755480A

公开(公告)日：1988-07-05

申请号：US930148

申请日：1986-11-12

Applicant: Leopoldo D. Yau ,  Shih-ou Chen ,  Yih S. Lin

Inventor： Leopoldo D. Yau ,  Shih-ou Chen ,  Yih S. Lin

IPC: H01L21/02 ,  H01L27/11 ,  H01C7/10 ,  H01L29/04

CPC classification number: H01L28/20 ,  H01L27/1112 ,  Y10S148/114 ,  Y10S148/136 ,  Y10S438/934

Abstract: An improved resistor for use in MOS integrated circuits. An opening is formed in an insulative layer which separates two conductive regions. A plasma enhanced chemical vapor deposition of passivation material such as silicon-rich silcon nitride is deposited in the window, contacting both conductive regions and providing resistance in a vertical direction between these regions.A subsequent annealing process involving controlled temperatures and cycle times provides for determining desired resistive values from an equivalent deposition process. Further, a barrier metal layer may be formed between the vertical resistor and the second conductive region.

Abstract translation: 一种用于MOS集成电路的改进型电阻器。 在分离两个导电区域的绝缘层中形成开口。 钝化材料如富硅锡烷氮化物的等离子体增强化学气相沉积沉积在窗口中，接触两个导电区域并在这些区域之间沿垂直方向提供电阻。 随后的涉及受控温度和循环时间的退火过程提供了从等效沉积工艺确定所需的电阻值。 此外，可以在垂直电阻器和第二导电区域之间形成阻挡金属层。

公开(公告)号：US4707909A

公开(公告)日：1987-11-24

申请号：US894416

申请日：1986-08-08

Applicant: Richard A. Blanchard

Inventor： Richard A. Blanchard

IPC: H01L21/02 ,  H01L21/324 ,  H01L21/477 ,  H01L27/00 ,  H01L31/00

CPC classification number: H01L28/20 ,  H01L21/324 ,  Y10S148/046 ,  Y10S148/071 ,  Y10S148/094 ,  Y10S148/136 ,  Y10T29/49082 ,  Y10T403/32598 ,  Y10T403/68

Abstract: A process of providing semi-insulating thin film resistors with closer tolerance values by furnance-annealing the film to increase is resistance to less than the final intended value, and then focused heat source-annealing the film to within a close tolerance of the final intended value.

Abstract translation: 通过对薄膜进行退火来提供具有更小的公差值的半绝缘薄膜电阻器的方法，其耐受性小于最终的预期值，然后将该聚焦热源退火到最终预期的紧公差内 值。

公开(公告)号：US4602421A

公开(公告)日：1986-07-29

申请号：US726558

申请日：1985-04-24

Applicant: Joseph Y. Lee ,  Michael H. Kriegel ,  Thomas Y. Chuh

Inventor： Joseph Y. Lee ,  Michael H. Kriegel ,  Thomas Y. Chuh

IPC: H01L21/02 ,  H01L21/30 ,  H01L21/477 ,  H01L21/26

CPC classification number: H01L28/20 ,  H01L21/3003 ,  Y10S148/136 ,  Y10T29/49082

Abstract: Low noise polycrystalline silicon resistors are fabricated in the following sequence:(1) deposit an appropriate thickness of polysilicon (e.g. 400 nm) on top of an oxidized wafer(2) resistor doping by ion implantation (e.g. phosphorous)(3) heavy doping of the end-contact regions of the polysilicon resistor by high-dose ion implantation(4) patterning the polysilicon resistor(5) oxidation/annealing the polysilicon resistor(6) open contacts to the polysilicon resistor(7) aluminum metallization to form ohmic contacts(8) a long (e.g. 3 hours) low temperature (e.g. at 375.degree.) pure hydrogen annealing to passivate the interface states in the polysilicon resistor. Polyresistors processed this way have a noise figure that is about a factor of three lower than samples processed otherwise. The low temperature post metallization annealing in pure hydrogen passivates the interfaces of polyresistors, reducing the l/f noise normally generated therein.

Abstract translation: 低噪声多晶硅电阻器按以下顺序制造：（1）在氧化晶片（2）上沉积适当厚度的多晶硅（例如400nm）（2）通过离子注入（例如磷）掺杂的电阻器（3）重掺杂 多晶硅电阻器的端接触区域通过高剂量离子注入（4）图案化多晶硅电阻器（5）来对多晶硅电阻器（6）进行氧化/退火，使多晶硅电阻器（7）的开路触点铝金属化以形成欧姆接触 8）长（例如3小时）低温（例如在375°）纯氢退火以钝化多晶硅电阻器中的界面态。 以这种方式处理的多晶体管的噪声系数比其他处理的样品低约三分之一。 纯氢气中的低温后金属化退火钝化了多晶硅的界面，降低了其中通常产生的l / f噪声。