公开(公告)号：US08427355B2

公开(公告)日：2013-04-23

申请号：US13232442

申请日：2011-09-14

申请人： Sai-Weng Sin ,  Li Ding ,  Yan Zhu ,  He-Gong Wei ,  Chi-Hang Chan ,  U-Fat Chio ,  Seng-Pan U ,  Rui Paulo da Silva Martins ,  Franco Maloberti

发明人： Sai-Weng Sin ,  Li Ding ,  Yan Zhu ,  He-Gong Wei ,  Chi-Hang Chan ,  U-Fat Chio ,  Seng-Pan U ,  Rui Paulo da Silva Martins ,  Franco Maloberti

IPC分类号： H03M1/38

CPC分类号： H03M1/1225 ,  H03M1/0695 ,  H03M1/1215 ,  H03M1/164 ,  H03M1/468

摘要： An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.

摘要翻译： 包括两个时间交错的逐次逼近寄存器（SAR）ADC的模数转换器（ADC）电路。 两个时间交织的SAR ADC中的每一个包括第一级SAR子ADC，残差放大器，第二级SAR子ADC和数字纠错逻辑。 剩余放大器在时间交织路径之间共享，具有减小的增益并且在子阈值中操作以实现功率有效设计。

公开(公告)号：US08390264B2

公开(公告)日：2013-03-05

申请号：US12729416

申请日：2010-03-23

申请人： Wen-Sheng Lin

发明人： Wen-Sheng Lin

IPC分类号： G05F3/08

CPC分类号： H03M1/0845 ,  H03M1/164 ,  H03M1/44

摘要： A differential reference voltage generator generates a first differential reference voltage and a second differential reference voltage. The differential reference voltage generator includes a first operational amplifier, a first transistor, a first resistor, and a second resistor. The first operational amplifier has a negative terminal adapted to receive a reference voltage. The first transistor has a source receiving a power supply voltage and has a gate electrically connected to an output terminal of the first operational amplifier. The first resistor has a first terminal electrically connected to a drain of the first transistor, and has a second terminal electrically connected to a positive terminal of the first operation amplifier. The second resistor has a first terminal electrically connected to the second terminal of the first resistor, and a second terminal electrically connect to a current mirror.

摘要翻译： 差分参考电压发生器产生第一差分参考电压和第二差分参考电压。 差分参考电压发生器包括第一运算放大器，第一晶体管，第一电阻器和第二电阻器。 第一运算放大器具有适于接收参考电压的负端子。 第一晶体管具有接收电源电压的源，并且具有电连接到第一运算放大器的输出端的栅极。 第一电阻器具有电连接到第一晶体管的漏极的第一端子，并且具有电连接到第一运算放大器的正极端子的第二端子。 第二电阻器具有电连接到第一电阻器的第二端子的第一端子和电连接到电流镜的第二端子。

公开(公告)号：US20130027231A1

公开(公告)日：2013-01-31

申请号：US13489865

申请日：2012-06-06

申请人： Daniel Meacham ,  Andrea Panigada ,  Jorge Grilo

发明人： Daniel Meacham ,  Andrea Panigada ,  Jorge Grilo

IPC分类号： H03M1/12

CPC分类号： H03M1/0673 ,  H03M1/0641 ,  H03M1/164

摘要： A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.

摘要翻译： 模数转换器（ADC）中的电路包括被配置为接收后端DAC的输出的放大器; 耦合到所述放大器的谐波失真校正电路（HDC），被配置为校正由于来自所述后端ADC的数字信号中存在的残余放大器的失真分量，所述HDC电路向加法器提供输出，所述加法器接收粗略的数字输出 来自粗略的ADC; 以及DAC噪声消除电路（DNC），其被配置为向所述加法器提供输出，其中所述DNC电路被配置为校正由于来自所述后端ADC的数字信号中存在的DAC的失真分量; 其中加法器的输出是ADC数字输出，并且其中ADC数字输出形成到HDC和DNC的输入。

公开(公告)号：US08362939B2

公开(公告)日：2013-01-29

申请号：US12999567

申请日：2009-06-11

申请人： Berry Anthony Johannus Buter ,  Hans Van De Vel

发明人： Berry Anthony Johannus Buter ,  Hans Van De Vel

IPC分类号： H03M1/38

CPC分类号： H03M1/0614 ,  G11C27/026 ,  H03M1/164 ,  H03M1/44

摘要： A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (IS) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.

摘要翻译： 公开了一种开关电容器流水线ADC级，其中包括复位开关以在采样周期的第一部分期间复位采样电容器。 因此，复位开关从而消除历史，并使采样基本上与所采集的先前采样无关，因此减少了码间干扰（IS）和由此产生的失真，而不会显着影响设备的采样周期或功率使用。

公开(公告)号：US08344927B2

公开(公告)日：2013-01-01

申请号：US12982547

申请日：2010-12-30

申请人： Young-deuk Jeon

发明人： Young-deuk Jeon

IPC分类号： H03M1/38

CPC分类号： H03M1/1019 ,  H03M1/1038 ,  H03M1/164

摘要： Provided are an analog digital converting device and a reference voltage controlling method thereof. The analog digital converting device includes: a first reference voltage generating circuit generating a first reference voltage; a second reference voltage generating circuit generating a second reference voltage; a first sub analog digital converter receiving an analog input signal and converting the analog input signal into a first digital signal by using the first reference voltage; an amplifier converting the first digital signal into a voltage corresponding to the first digital signal by using the first reference voltage and amplifying a difference between a voltage level of the analog input signal and a voltage level corresponding to the first digital signal to output a residual signal; and a second sub analog digital converter receiving the residual signal and converting the residual signal into a second digital signal by using the second reference voltage.

摘要翻译： 提供了一种模拟数字转换装置及其参考电压控制方法。 模拟数字转换装置包括：产生第一参考电压的第一参考电压产生电路; 产生第二参考电压的第二参考电压产生电路; 接收模拟输入信号并通过使用第一参考电压将模拟输入信号转换为第一数字信号的第一子模拟数字转换器; 放大器，通过使用第一参考电压将第一数字信号转换成对应于第一数字信号的电压，并放大模拟输入信号的电压电平与对应于第一数字信号的电压电平之差，以输出残留信号 ; 以及第二子模拟数字转换器，其接收残余信号，并且通过使用第二参考电压将残差信号转换成第二数字信号。

公开(公告)号：US08274419B2

公开(公告)日：2012-09-25

申请号：US12702970

申请日：2010-02-09

申请人： Hugo Gicquel ,  Sophie Minot ,  Marc Sabut

发明人： Hugo Gicquel ,  Sophie Minot ,  Marc Sabut

IPC分类号： H03M1/42

CPC分类号： H03M1/164 ,  H03M1/187 ,  Y10T29/49002

摘要： A device may include a programmable gain amplifier and an analog-digital converter with pipeline architecture having several stages. The first stage of the analog-digital converter may incorporate the programmable gain amplifier and an analog-digital conversion circuit with a programmable threshold.

摘要翻译： 器件可以包括可编程增益放大器和具有多级的管线架构的模数转换器。 模数转换器的第一级可以结合可编程增益放大器和具有可编程阈值的模数转换电路。

公开(公告)号：US08184033B2

公开(公告)日：2012-05-22

申请号：US12778875

申请日：2010-05-12

申请人： Charles Chang-I Wang ,  Ivan Richard Linscott ,  Umran S. Inan

发明人： Charles Chang-I Wang ,  Ivan Richard Linscott ,  Umran S. Inan

IPC分类号： H03M1/38

CPC分类号： H03M1/0602 ,  H03M1/0827 ,  H03M1/1033 ,  H03M1/164

摘要： Techniques for an analog-to-digital converter (ADC) using pipeline architecture includes a linearization technique for a spurious-free dynamic range (SFDR) over 80 deciBels. In some embodiments, sampling rates exceed a megahertz. According to a second approach, a switched-capacitor circuit is configured for correct operation in a high radiation environment. In one embodiment, the combination yields high fidelity ADC (>88 deciBel SFDR) while sampling at 5 megahertz sampling rates and consuming

摘要翻译： 使用流水线架构的模数转换器（ADC）的技术包括一个超过80比特的无杂散动态范围（SFDR）的线性化技术。 在一些实施例中，采样速率超过兆赫兹。 根据第二种方法，开关电容器电路被配置为在高辐射环境中正确操作。 在一个实施例中，组合产生高保真ADC（> 88 deciBel SFDR），同时以5兆赫采样率采样并消耗<60毫瓦。 此外，即使采用商业化的0.25-μmCMOS技术（1μm= 12-6米）制造，它在恶劣的辐射环境中保持这种性能。 具体来说，所述性能通过最高测试的2兆拉德（Si）总剂量持续，并且ADC在升高的温度（131摄氏度）下显示没有闭锁，达到6300万电子伏特平方厘米/毫升的最高测试线性能量转移。 ）和电源（2.7伏，相对于2.5伏标称）。

公开(公告)号：US20120098684A1

公开(公告)日：2012-04-26

申请号：US13242675

申请日：2011-09-23

申请人： Roger Petigny ,  Hugo Gicquel ,  Sophie Minot

发明人： Roger Petigny ,  Hugo Gicquel ,  Sophie Minot

IPC分类号： H03M1/06

CPC分类号： H03M1/1047 ,  H03M1/164

摘要： Device for processing an analogue signal, comprising an analogue-digital converter with a pipelined architecture having an offset, and compensation means configured to compensate for the said offset, the said compensation means comprising digital correction means configured to correct the integer portion of the offset based on the digital signal delivered by the analogue-digital converter, and analogue correction means included in the last stage of the analogue-digital converter and configured to correct the decimal portion of the offset.

摘要翻译： 用于处理模拟信号的装置，包括具有偏移的流水线架构的模拟数字转换器，以及被配置为补偿所述偏移的补偿装置，所述补偿装置包括数字校正装置，被配置为校正基于偏移的整数部分 对由模拟数字转换器传送的数字信号和模拟数字转换器的最后级中包括的模拟校正装置进行校正，并且被配置为校正偏移的小数部分。

公开(公告)号：US20120092202A1

公开(公告)日：2012-04-19

申请号：US13060720

申请日：2009-09-01

申请人： Nikolaos Petrellis ,  Michael Birbas ,  John Kikidis

发明人： Nikolaos Petrellis ,  Michael Birbas ,  John Kikidis

IPC分类号： H03M1/12

CPC分类号： H03M1/368 ,  H03M1/146 ,  H03M1/164 ,  H03M1/366 ,  H03M1/42

摘要： An analog to digital converter for converting an initial analog signal into a digital signal comprising at least one electronic module with an input, a first output, and a second output, which module generates from an analog input signal: a first output signal, which first output signal in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the integer quotient of division of the input signal by a number or comprises a plurality of signals which if combined are substantially equal to the integer quotient of division of the input signal in terms of multiples of a predetermined amount of current or voltage, and a second output signal which in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the remainder of the division, the analog to digital converter also comprising a further analog to digital converter for converting the second output signal into a digital signal, wherein the further analog to digital converter is connected the at least one module and the module is configured so that in use when the analog input signal connects through the input the first output signal connects through the first output, and the second output signal connects through the second output into the further analog to digital converter.

摘要翻译： 一种模数转换器，用于将初始模拟信号转换成数字信号，该数字信号包括至少一个电子模块，该输入，第一输出和第二输出由模拟输入信号产生：第一输出信号，第一输出信号 输出信号以预定量的电流或电压（例如1uA或1mV）的倍数基本上等于输入信号除数的整数商，或包括多个信号，如果被组合为基本上 等于以预定量的电流或电压的倍数的输入信号的除法的整数商和以预定量的电流或电压（例如1uA或1mV）的倍数的第二输出信号 ，基本上等于除法的剩余部分，模数转换器还包括另外的模数转换器，用于将第二输出信号转换为数字 信号，其中所述另外的模数转换器连接到所述至少一个模块，并且所述模块被配置为使得当模拟输入信号通过输入连接时，第一输出信号通过第一输出连接，并且第二输出信号连接 通过第二个输出进一步的模数转换器。

公开(公告)号：US20120062402A1

公开(公告)日：2012-03-15

申请号：US12880311

申请日：2010-09-13

申请人： Robert F. Payne

发明人： Robert F. Payne

IPC分类号： H03M1/00

CPC分类号： H03M1/0872 ,  H03M1/1215 ,  H03M1/1225 ,  H03M1/164 ,  H03M1/44

摘要： In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths.

摘要翻译： 在使用以小于50％工作周期工作的放大器的许多应用中，减少数量放大器以降低功耗将是有利的。 这里，提供了一种放大器，其被时分复用以容纳多个数据路径。 此外，在该放大器的输出端子处提供复位电路或复位机构，以短暂地输出端子短路，以防止可能由数据路径之间切换引起的毛刺。