公开(公告)号：US20080191736A1

公开(公告)日：2008-08-14

申请号：US12050897

申请日：2008-03-18

Applicant: Jason Redgrave ,  Teju Khubchandani

Inventor： Jason Redgrave ,  Teju Khubchandani

IPC: H03K19/173

CPC classification number: H03K19/17776 ,  G06F7/32 ,  G06F7/764 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17764

Abstract: Some embodiments of the invention provide configurable integrated circuit (IC) that includes several configurable circuits that are conceptually in tiles. The IC also includes a first data network for passing data between the configurable circuits. The IC further includes a second packet-switch network for receiving packets of data from the outside of the configurable IC and switchably routing each packet to at least one destination tile. In some embodiments, the second packet-switch network supplies data from the tiles that the configurable circuits output in response to data packets received from outside of the configurable IC. Also, in some embodiments a particular packet that is for a particular resource in a particular tile includes a first address that identifies the particular configurable tile from the plurality of configurable tiles, and then a second address that identifies the particular resource within the particular configurable tile.

Abstract translation: 本发明的一些实施例提供了可配置集成电路（IC），其包括概念上在瓦片中的几个可配置电路。 IC还包括用于在可配置电路之间传递数据的第一数据网络。 IC还包括第二分组交换网络，用于从可配置IC的外部接收数据分组，并且可切换地将每个分组路由到至少一个目的地分块。 在一些实施例中，第二分组交换网络响应于从可配置IC的外部接收的数据分组提供可配置电路输出的瓦片中的数据。 此外，在一些实施例中，用于特定瓦片中的特定资源的特定分组包括识别来自多个可配置分块的特定可配置分块的第一地址，然后标识特定可配置分块内的特定资源的第二地址 。

公开(公告)号：US07362132B2

公开(公告)日：2008-04-22

申请号：US11524386

申请日：2006-09-21

Applicant: Kazuaki Imafuku

Inventor： Kazuaki Imafuku

IPC: H03K19/173

CPC classification number: H03K19/17776 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17772

Abstract: A reconfigurable integrated circuit device which is configured to an arbitrary computation state based on configuration data has a reconfiguration circuit unit, having a plurality of processor elements which are reconfigurable and a processor element network which connects the processor elements in an arbitrary state; and, a configuration control section, which supplies configuration data to the processor elements and to the processor element network, to configure the reconfiguration circuit unit in an arbitrary state. In response to reset, at least a portion of the reconfiguration circuit unit is configured as a memory initialization circuit which writes initial values to internal memory or to external memory, and, after completion of operation of the memory initialization circuit, the configuration control section begins supplying the configuration data.

Abstract translation: 配置为基于配置数据的任意计算状态的可重构集成电路装置具有重配置电路单元，其具有可重配置的多个处理器元件和以任意状态连接处理器元件的处理器元件网络; 以及配置控制部分，其将配置数据提供给处理器元件和处理器元件网络，以将重新配置电路单元配置为任意状态。 响应于复位，重配置电路单元的至少一部分被配置为将初始值写入内部存储器或外部存储器的存储器初始化电路，并且在完成存储器初始化电路的操作之后，配置控制部分开始 提供配置数据。

公开(公告)号：US07358762B1

公开(公告)日：2008-04-15

申请号：US11131764

申请日：2005-05-18

Applicant: James A. Walstrum, Jr. ,  Steven K. Knapp ,  Wayne E. Wennekamp

Inventor： James A. Walstrum, Jr. ,  Steven K. Knapp ,  Wayne E. Wennekamp

IPC: H03K19/173

CPC classification number: H03K19/17776 ,  H03K19/17744 ,  H03K19/17748

Abstract: An interface between a programmable device and an external device coupled to the programmable device is described. The interface includes configurable control pins for providing control signals to the external device. The programmable device may be a field programmable gate array and the external device may be a nonvolatile memory. In some cases, the interface may be used to provide a byte-wide, or other parallel, interface. After configuration, the pins of the interface may be reclaimed and used for other purposes, such as accessing one or more external memories or other devices connected to a bus.

Abstract translation: 描述了可编程设备和耦合到可编程设备的外部设备之间的接口。 该接口包括用于向外部设备提供控制信号的可配置控制引脚。 可编程器件可以是现场可编程门阵列，并且外部器件可以是非易失性存储器。 在某些情况下，该接口可用于提供字节范围或其他并行接口。 在配置之后，接口的引脚可以被回收并用于其他目的，例如访问一个或多个外部存储器或连接到总线的其他设备。

公开(公告)号：US07345505B2

公开(公告)日：2008-03-18

申请号：US11400122

申请日：2006-04-10

Applicant: Raminda Udaya Madurawe

Inventor： Raminda Udaya Madurawe

IPC: H03K19/173

CPC classification number: H03K19/17776 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/115 ,  H01L27/118 ,  H03K19/1776 ,  H03K19/17796

Abstract: A highly economical alterable ASIC implements partitioned segments of an ASIC design in a smaller Silicon foot-print, each segment utilizing the entire IC. The device is able to switch quickly between the multiple segments with global control signals, without incurring long delays to reconfigure configuration memory. The alterable ASIC comprises programmable logic blocks and a configuration circuit with multiple sets of configuration memory, each set programmed to hold an optimized segment. Either random access memory (RAM) or mask configured read only memory (ROM) store the partitioned segments.

Abstract translation: 高度经济的可变ASIC在较小的硅脚印中实施ASIC设计的分割段，每段利用整个IC。 该设备能够在具有全局控制信号的多个段之间快速切换，而不会导致长时间延迟重新配置配置存储器。 可变ASIC包括可编程逻辑块和具有多组配置存储器的配置电路，每组配置存储器被设置为保持优化段。 随机存取存储器（RAM）或掩膜配置的只读存储器（ROM）存储分区段。

公开(公告)号：US20070279087A1

公开(公告)日：2007-12-06

申请号：US11524386

申请日：2006-09-21

Applicant: Kazuaki Imafuku

Inventor： Kazuaki Imafuku

IPC: H03K19/173

CPC classification number: H03K19/17776 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17772

Abstract: A reconfigurable integrated circuit device which is configured to an arbitrary computation state based on configuration data has a reconfiguration circuit unit, having a plurality of processor elements which are reconfigurable and a processor element network which connects the processor elements in an arbitrary state; and, a configuration control section, which supplies configuration data to the processor elements and to the processor element network, to configure the reconfiguration circuit unit in an arbitrary state. In response to reset, at least a portion of the reconfiguration circuit unit is configured as a memory initialization circuit which writes initial values to internal memory or to external memory, and, after completion of operation of the memory initialization circuit, the configuration control section begins supplying the configuration data.

Abstract translation: 配置为基于配置数据的任意计算状态的可重构集成电路装置具有重配置电路单元，其具有可重配置的多个处理器元件和以任意状态连接处理器元件的处理器元件网络; 以及配置控制部分，其将配置数据提供给处理器元件和处理器元件网络，以将重新配置电路单元配置为任意状态。 响应于复位，重配置电路单元的至少一部分被配置为将初始值写入内部存储器或外部存储器的存储器初始化电路，并且在完成存储器初始化电路的操作之后，配置控制部分开始 提供配置数据。

公开(公告)号：US07301822B1

公开(公告)日：2007-11-27

申请号：US11131751

申请日：2005-05-18

Applicant: James A. Walstrum, Jr. ,  Wayne E. Wennekamp ,  Eric E. Edwards

Inventor： James A. Walstrum, Jr. ,  Wayne E. Wennekamp ,  Eric E. Edwards

IPC: G11C7/10

CPC classification number: H03K19/17776 ,  G11C7/20 ,  H03K19/17748 ,  H03K19/17772

Abstract: A programmable device having a multi-boot capability is described. The programmable device may initially load first configuration data for configuring programmable resources of the device. Thereafter, a multi-boot operation may be triggered, causing the device to reconfigure and load second configuration data. Prior to loading the second configuration data, the device may store status information. In some cases, further multi-boot operations may be triggered for loading other configuration data.

Abstract translation: 描述具有多引导能力的可编程设备。 可编程设备可以初始地加载用于配置设备的可编程资源的第一配置数据。 此后，可以触发多引导操作，导致设备重新配置并加载第二配置数据。 在加载第二配置数据之前，设备可以存储状态信息。 在某些情况下，可能会触发进一步的多引导操作来加载其他配置数据。

公开(公告)号：US07301821B1

公开(公告)日：2007-11-27

申请号：US11251074

申请日：2005-10-13

Applicant: Jonathan Greene ,  Robert M. Salter, III

Inventor： Jonathan Greene ,  Robert M. Salter, III

IPC: G11C16/04

CPC classification number: G11C16/0433 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/3431 ,  G11C29/50 ,  H03K19/17776 ,  H03K19/1778

Abstract: A method for storing data on nodes in memory cells of a non-volatile memory cell array including steps of setting non-volatile devices of the non-volatile memory cell array to a desired state, biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array to an off state, loading data onto column lines of the non-volatile memory cell array and biasing non-volatile devices in a second set of rows in the memory cells of the non-volatile memory cell array to store data from the column lines on the nodes in the memory cells of the non-volatile memory cell array.

Abstract translation: 一种用于将数据存储在非易失性存储单元阵列的存储单元中的节点的方法，包括将非易失性存储单元阵列的非易失性设备设置为期望状态的步骤，将上拉设备和非易失性设备偏置 所述非易失性存储单元阵列的第一组行到关闭状态，将数据加载到所述非易失性存储单元阵列的列线上并且偏置所述非易失性存储单元阵列的存储单元中的第二组行中的非易失性设备， 非易失性存储单元阵列，用于存储来自非易失性存储单元阵列的存储单元中节点上列列的数据。

公开(公告)号：US20070245288A1

公开(公告)日：2007-10-18

申请号：US11081854

申请日：2005-03-15

Applicant: Andre Rohe ,  Steven Teig

Inventor： Andre Rohe ,  Steven Teig

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17776

Abstract: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and an end operation, the method assigns a particular operation in the first set to a first operational cycle based at least partially on the position of the particular operation with respect to the start and end operations.

Abstract translation: 一些实施例提供了一种用多个可配置电路设计可配置集成电路（“IC”）的方法。 该方法接收具有用于可配置电路的多组操作的设计以在不同的操作周期中执行的设计。 对于至少具有开始操作和结束操作的第一组操作，该方法至少部分地基于特定操作相对于开始的位置而将第一组中的特定操作分配到第一操作周期，以及 结束操作。

公开(公告)号：US20070075733A1

公开(公告)日：2007-04-05

申请号：US11162997

申请日：2005-09-30

Applicant: Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

Inventor： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

IPC: H03K19/177

CPC classification number: H03K19/17776 ,  H03K19/17732 ,  H03K19/17756 ,  H03K19/17772

Abstract: A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

Abstract translation: 包括基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）装置。 非基于编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而节省加电时的处理时间。 公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和齐平扫描电路。 还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。 除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

公开(公告)号：US07193432B1

公开(公告)日：2007-03-20

申请号：US10882579

申请日：2004-06-30

Applicant: Herman Schmit ,  Steven Teig

Inventor： Herman Schmit ,  Steven Teig

IPC: H03K19/173 ,  H03K19/177 ,  G06F7/38 ,  H01L25/00

CPC classification number: H03K19/17756 ,  H03K19/17776 ,  H03K19/17796

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes first and second circuits. The first circuit is a logic circuit for receiving configuration data sets and performing at least a first function when receiving a first configuration data set and a second function when receiving a second configuration data set. The second circuit communicatively couples to the first logic circuit. The second circuit is for supplying configuration data sets to the first logic circuit. The second circuit has a first set of input terminals. The integrated circuit also has a second set of input terminals for carrying data. Several the second set of input terminals overlap several of the first set of input terminals. The IC also has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set.

Abstract translation: 本发明的一些实施例提供了一种可配置的集成电路（IC）。 IC包括第一和第二电路。 第一电路是用于接收配置数据集并且当接收第二配置数据集时接收第一配置数据集和第二功能时执行至少第一功能的逻辑电路。 第二电路通信耦合到第一逻辑电路。 第二电路用于将配置数据组提供给第一逻辑电路。 第二电路具有第一组输入端子。 集成电路还具有用于承载数据的第二组输入端子。 几个第二组输入端与第一组输入端重叠。 IC还具有一组通孔，其中每个通孔将第一组中的输入端与第二组中的输入端连接。