公开(公告)号：US4213103A

公开(公告)日：1980-07-15

申请号：US904413

申请日：1978-05-10

申请人： David R. Birt

发明人： David R. Birt

IPC分类号： H03K5/02 ,  H03K5/151 ,  H03K7/08 ,  H03K17/66 ,  H04B1/04 ,  H04B1/16 ,  H03K7/10 ,  H02M7/48

CPC分类号： H03K7/08 ,  H03K17/662 ,  H03K5/023 ,  H03K5/1515 ,  H04B1/1607 ,  H04B1/04

摘要： A switching system is described for use in for example AM transmitters comprising at least one pair of semi-conductor output switches connected in series across an AM modulated D.C. supply and arranged to be operated sequentially by a series of "on" and "off" command signals to energize a load, such as an antenna. The circuitry provides a delay interval between the "off" command to any one switch and the "on" command to the next switch in the sequence. Means are provided for detecting when two successive switches in the sequence conduct simultaneously, and means are provided for increasing the duration of the delay interval when such simultaneous conduction is detected.

摘要翻译： 描述了用于例如AM发射机的开关系统，其包括跨AM调制DC电源串联连接的至少一对半导体输出开关并且被布置成通过一系列“开”和“关”命令顺序地操作 信号来激励负载，例如天线。 电路在“断开”命令与任何一个开关之间提供延迟间隔，并在序列中向下一个开关提供“开”命令。 提供用于检测序列中的两个连续的开关同时导通的装置，并且提供用于在检测到这种同时传导时增加延迟间隔的持续时间的装置。

公开(公告)号：US3710147A

公开(公告)日：1973-01-09

申请号：US3710147D

申请日：1971-06-29

申请人： PLESSEY HANDEL INVESTMENT AG

发明人： LEE M

IPC分类号： H03K17/10 ,  H03K17/66 ,  H03K17/56

CPC分类号： H03K17/662 ,  H03K17/10 ,  H03K17/666

摘要： A high voltage switch arrangement comprising switches each defined by cascaded transistors connected effectively in the arms of a bridge for switching a high voltage across a capacitive load so that an a.c. voltage is supplied through the load when the bridge is fed from a d.c. source and the switches operated sequentially.

摘要翻译： 一种高电压开关装置，包括开关，每个开关由层叠的晶体管限定，该晶体管有效连接在桥臂中，用于在电容性负载上切换高电压， 当电桥从直流电源供电时，通过负载提供电压。 源和开关顺序操作。

公开(公告)号：US3680048A

公开(公告)日：1972-07-25

申请号：US3680048D

申请日：1970-03-04

申请人： TDK ELECTRONICS CO LTD

发明人： EZAKI JOICHIRO

IPC分类号： G11C11/06 ,  H03K17/041 ,  H03K17/66 ,  H04Q9/00

CPC分类号： H03K17/662 ,  G11C11/06007 ,  H03K17/04113

摘要： A read/write drive circuit for a circuit having a driver and a plurality of read/write circuit units connected in parallel thereto, wherein when one desired circuit unit is driven with a potential of one polarity, a potential of the opposite polarity is applied to other circuit units, thereby preventing a flow of current through the other circuit units and through an inadvertent ground path including stray capacitances. A higher speed operation is feasible because no charging current flows through the other circuit units that are not driven.

摘要翻译： 一种用于具有驱动器和多个并行连接的读/写电路单元的电路的读/写驱动电路，其中当一个所需的电路单元以一极性的电位驱动时，相反极性的电位被施加到 从而防止电流流过其它电路单元并通过包括杂散电容的无意的接地路径。 由于没有充电电流流过未被驱动的其他电路单元，因此更高的速度操作是可行的。

公开(公告)号：US3624413A

公开(公告)日：1971-11-30

申请号：US3624413D

申请日：1969-10-01

申请人： DAVID K FORD

发明人： FORD DAVID K

IPC分类号： H03K5/08 ,  H03K17/62 ,  H03K17/66 ,  H03K17/00

CPC分类号： H03K17/662 ,  H03K5/08 ,  H03K17/6285

摘要： A phase or polarity selective electronic control or amplification circuit requiring no reactive components and capable of transforming a single-ended input signal into out-ofphase output signals. The circuit includes switching or gating means to which the input signal is applied and which control one or more output circuit means. When an input signal of a first phase is applied to the switching or gating means, one or more output circuit means are permitted to pass current. When an input signal of another phase is applied, other output circuit means are permitted to pass current. The output circuit means can be connected to separate loads so that the particular load energized is determined by the phase of the input signal. Alternatively, the output circuit means can be connected to a single load so that the direction of current flow through that load is determined by the phase of the input signal, as in a push-pull amplifier.

公开(公告)号：US3396292A

公开(公告)日：1968-08-06

申请号：US43719465

申请日：1965-03-04

申请人： HOLLANDSE SIGNAALAPPARATEN BV

发明人： JAN LANSINK GERRIT

IPC分类号： H02H11/00 ,  H03K3/26 ,  H03K17/0814 ,  H03K17/62 ,  H03K17/66

CPC分类号： H03K17/08146 ,  H02H11/00 ,  H03K3/26 ,  H03K17/6285 ,  H03K17/662

公开(公告)号：US3350572A

公开(公告)日：1967-10-31

申请号：US35738164

申请日：1964-04-06

申请人： GEN ELECTRIC

发明人： MORGAN RAYMOND E

IPC分类号： H02M3/156 ,  H03K3/30 ,  H03K3/315 ,  H03K3/45 ,  H03K17/60 ,  H03K17/66

CPC分类号： H03K3/30 ,  H02M3/156 ,  H03K3/315 ,  H03K3/45 ,  H03K17/60 ,  H03K17/601 ,  H03K17/662

公开(公告)号：US20080180158A1

公开(公告)日：2008-07-31

申请号：US12022716

申请日：2008-01-30

申请人： Rosario Scollo ,  Massimo Nania

发明人： Rosario Scollo ,  Massimo Nania

IPC分类号： H03K17/60

CPC分类号： H03K17/567 ,  H03K17/0406 ,  H03K17/06 ,  H03K17/662 ,  H03K17/6871

摘要： A driving circuit for an emitter-switching configuration of transistors having first and second control terminals connected to the driving circuit, forms a controlled emitter-switching device having in turn respective collector, source and gate terminals. The driving circuit comprises a driving block coupled between the collector terminal and the source terminal of the controlled emitter-switching device and connected to the first control terminal of the emitter-switching configuration. Further advantageously, the driving block comprises at least one IGBT driving device coupled between the collector terminal and the first control terminal of the emitter-switching configuration and having, in turn, a third control terminal, as well as a driving bipolar transistor, coupled between the collector terminal and the first control terminal of the emitter-switching configuration for controlling a saturation condition of said bipolar transistor of said emitter-switching configuration maintaining a base-collector junction thereof at a voltage next to zero and having, in turn, a fourth control terminal.

摘要翻译： 用于具有连接到驱动电路的第一和第二控制端子的晶体管的发射极 - 开关配置的驱动电路形成受控的发射极开关器件，其依次具有集电极，源极和栅极端子。 驱动电路包括耦合在受控发射极开关器件的集电极端子和源极端子之间并连接到发射极开关配置的第一控制端子的驱动块。 进一步有利地，驱动块包括耦合在发射极 - 开关配置的集电极端子和第一控制端子之间的至少一个IGBT驱动器件，并且具有连接在第三控制端子之间的第三控制端子以及驱动双极晶体管 集电极端子和发射极开关配置的第一控制端子，用于控制所述发射极 - 开关配置的所述双极晶体管的饱和状态，将其基极集电极结保持在零下的电压，并且又具有第四 控制终端。

公开(公告)号：US20040120065A1

公开(公告)日：2004-06-24

申请号：US10404531

申请日：2003-03-31

发明人： Hiroshi Takeuchi

IPC分类号： G11B005/02 ,  G11B005/09

CPC分类号： G11B5/022 ,  G11B5/012 ,  G11B5/035 ,  G11B5/09 ,  G11B2005/001 ,  G11B2005/0013 ,  H03K17/16 ,  H03K17/662

摘要： Embodiments of the present invention relate to an impedance-matched write driver circuit which comprises a voltage source, a write driver circuit electrically coupled to the voltage source, a signal input coupled so as to effect the output of the write driver circuit, and an impedance matching circuit electrically coupled to the write driver circuit, wherein the impedance matching circuit is enabled to damp the output oscillations in the output of the write driver circuit. Importantly, the impedance of the impedance-matched write driver circuit is selectable by component selection or by logic. Another embodiment of the present invention is directed to a system, e.g., a magnetic disk storage unit that makes use of the write driver as described herein.

摘要翻译： 本发明的实施例涉及一种阻抗匹配写入驱动器电路，其包括电压源，电耦合到电压源的写入驱动器电路，耦合以便实现写入驱动器电路的输出的信号输入和阻抗 电耦合到写驱动器电路的匹配电路，其中阻抗匹配电路能够抑制写驱动器电路的输出中的输出振荡。 重要的是，阻抗匹配的写入驱动器电路的阻抗可以通过元件选择或逻辑来选择。 本发明的另一实施例涉及一种系统，例如使用如本文所述的写入驱动器的磁盘存储单元。

公开(公告)号：US06373298B1

公开(公告)日：2002-04-16

申请号：US09772770

申请日：2001-01-30

申请人： Patrick Teterud ,  Thomas Van Eaton

发明人： Patrick Teterud ,  Thomas Van Eaton

IPC分类号： H03K300

CPC分类号： H03K17/04166 ,  H03K17/567 ,  H03K17/662

摘要： A HDD write driver circuit (30) having two sets of boost devices (Q1, M2, and Q2, M1) which are temporarily turned on during a current reversal to boost the normal current and increase the differential transient voltage across the coil (LS) while decreasing the TRTF. During a current reversal cycle, one set of transistors is turned on while the other set is left off. The on set to pulls the node at one end of the coil substantially to the positive rail, and pulls the other node at the other end of the coil substantially to the lower rail (Vee). The boost FETs (M1, M2) are preferably large PMOS devices that must be driven hard to achieve a quick transient switching time. Advantageously, when one of the PMOS FETs (M1, M2) are on, the associated series resistor (RS) is bypassed. The voltage at nodes HX and HY are no longer limited by an IR voltage drop associated with a resister (RS) therefore increasing the differential transient voltage across nodes HX and HY by increasing the maximum transient voltage of the pull-up node. Preferably, each node (HX, HY) of the coil (LS) can be pulled to within 0.2 volts of the positive rail.

摘要翻译： 一种具有两组升压装置（Q1，M2和Q2，M1）的HDD写入驱动器电路（30），其在电流反向期间暂时导通，以升高正常电流并增加线圈（LS）两端的差动瞬态电压， 同时减少TRTF。 在电流反转周期期间，一组晶体管导通，而另一组晶体管关闭。 该线圈将线圈的一端的节点基本上拉至正导轨，并将线圈另一端的另一节点基本拉到下导轨（Vee）。 升压FET（M1，M2）优选是必须被驱动以实现快速瞬态切换时间的大型PMOS器件。 有利的是，当一个PMOS FET（M1，M2）导通时，相关的串联电阻（RS）被旁路。 节点HX和HY处的电压不再受与电阻（RS）相关联的IR电压降限制，因此通过增加上拉节点的最大瞬态电压来增加节点HX和HY两端的差分瞬态电压。 优选地，线圈（LS）的每个节点（HX，HY）可以被拉到正轨的0.2伏以内。

公开(公告)号：US06246269B1

公开(公告)日：2001-06-12

申请号：US09283154

申请日：1999-04-01

申请人： John A. Schuler ,  Craig M. Brannon

发明人： John A. Schuler ,  Craig M. Brannon

IPC分类号： H03K300

CPC分类号： G11B5/022 ,  G11B5/02 ,  G11B20/10009 ,  G11B20/10037 ,  G11B2005/0013 ,  H03K17/16 ,  H03K17/662

摘要： A programmable current source is provided for an H-switch to dampen overshoot resulting from a drop in voltage at a node during data transitions. The programmable current source is connected to both nodes of the H-switch on each side of the write head and is responsive to a voltage drop to below a threshold voltage at one node to injecting current into the one node during the period that the node voltage is below the threshold voltage. Preferably, a second programmable current source is connected to both nodes and is responsive to a voltage rise to above a second threshold voltage at the one of the nodes to sink current from the node to dampen undershoot.

摘要翻译： 为H开关提供可编程电流源，以阻止由数据转换期间节点处的电压降低而产生的过冲。 可编程电流源连接到写头的每侧的H开关的两个节点，并且响应于在一个节点处的电压降低于阈值电压以在节点电压的时段期间将电流注入到一个节点 低于阈值电压。 优选地，第二可编程电流源连接到两个节点，并且响应于在所述节点之一处的电压上升到高于第二阈值电压以从节点吸收电流以抑制下冲。