Abstract:
A computer arrangement with a processor (5) and at least one memory unit (7, 9, 11, 13) connected to the processor (5) and including dynamic random access memory (13), wherein the computer arrangment is arranged to use but not to refresh at least part of the dynamic random access memory (13) while running a program.
Abstract:
Upon receiving a read command from an external device, a control element in an IC card determines whether transmission data to be stored in a transmission buffer area is the data that has been read out from a transfer permission area. When determining in the determination that the data is the data that has been read out from the transfer permission area, the control element stores the data in the transmission buffer area and then outputs it to the outside as a response to the read command. On the other hand, when determining in the above determination that the data is not the data that has been read out from the transfer permission area, the control element aborts the operation.
Abstract:
A system for open electronic commerce having a customer trusted agent securely communicating with a first money module, and a merchant trusted agent securely communicating with a second money module. Both trusted agents are capable of establishing a first cryptographically secure session, and both money modules are capable of establishing a second cryptographically secure session. The merchant trusted agent transfers electronic merchandise to the customer trusted agent, and the first money module transfers electronic money to the second money module. The money modules inform their trusted agents of the successful completion of payment, and the customer may use the purchased electronic merchandise.
Abstract:
A computer arrangement with a processor (5) and at least one memory unit (7, 9, 11, 13) connected to the processor (5) and including dynamic random access memory (13), wherein the computer arrangment is arranged to use but not to refresh at least part of the dynamic random access memory (13) while running a program.
Abstract:
The invention relates to a method for storing information in information storage means of a security module and for operating on information units in a security module, and the associated security module, wherein two storage areas (41, 42) are defined, one of which (41) is for storing the information (a, b, c; d, e, f) in dispersed pieces (a, b, c), (d, e, f), the other of which (42) is for storing addresses (AA, 92) at which the pieces of information are located. The storage in the second storage area takes place in positions that are based on the addresses (83, 86) of the pieces of information in the first storage area (41), as defined before dispersion.
Abstract:
A method is described for authenticating a portable object that includes a processor and a memory. The memory contains at least one code defining operations capable of being executed by the portable object, as well as a one-way function. The method comprises an authentication of the portable object which includes sending the portable object an order so that the latter executes a calculation of a result by applying to the one way function at least part of the code. This result enters into the implementation of a given operation, the operation being performed successfully only when the portable object is authentic.
Abstract:
The aim of this invention is to improve in an optimal way the security of smart cards to prevent the fraudulent control of a cryptographic processor(s) by means of external signals that interfere with the normal development of the tasks of a processor(s). This aim is reached by a component IC of a security module comprising at least two processors CPU A, CPU B each connected to program memories ROM A, ROM B, to non-volatile programmable and erasable memories (EEPROM) EEPROM A, EEPROM B containing the data and random access memories (RAM) RAM A, RAM B that serve as temporary data storage during processing, the first processor CPU A having an interface bus with the exterior of the component IC, characterized in that the second processor CPU B is connected to the first processor CPU A through an exchange memory DPR, the non-volatile programmable and erasable memory EEPROM A of the first processor CPU A having read-only access R for said first processor CPU A, the second processor CPU B having read and write access R/W on said non-volatile programmable and erasable memory EEPROM A of the first processor CPU A.
Abstract:
A ID circuit produces a unique binary identification code (ID) for each integrated circuit in which it is implemented by setting states of each bit of the ID as a function of random variations in material forming the IC that occur at the time the IC is fabricated. The ID circuit includes an ID generating circuit for generating the ID, a non-volatile memory, and a control circuit for writing the ID generated by the ID generating circuit into the non-volatile memory in response to a first occurrence of a write cue event. Thereafter the control circuit responds to each occurrence of a read cue event by reading the ID out of the non-volatile memory and providing it as an IC output.
Abstract:
In accordance with an embodiment of the present invention, an electronic device is displayed for purchase by a user and includes a controller and a protected area for storing a key and a bar code associated with and for identifying the device including a password unique to the device, wherein upon purchase of the device, the password is compared to the key and upon successful activation thereof, the device is activated, otherwise, the device is rendered inoperable.
Abstract:
A digital signature scheme for a “smart” card utilizes a set of prestored signing elements and combines pairs of the elements to produce a new session pair. The combination of the elements is performed partly on the card and partly on the associated transaction device so that the exchange of information between card and device does not disclose the identity of the signing elements. The signing elements are selected in a deterministic but unpredictable manner so that each pair of elements is used once. Further signing pairs are generated by implementing the signing over an anomalous elliptic curve encryption scheme and applying a Frobenius Operator to the normal basis representation of one of the elements.