公开(公告)号：US20130234749A1

公开(公告)日：2013-09-12

申请号：US13884882

申请日：2011-11-10

Applicant: Masamitsu Honda ,  Satoshi Isofuku ,  Hideki Arai

Inventor： Masamitsu Honda ,  Satoshi Isofuku ,  Hideki Arai

IPC: G01R31/28

CPC classification number: G01R31/2879 ,  G01R29/0814 ,  G01R31/001 ,  G01R31/312

Abstract: In a testing apparatus, an electronic equipment to be an equipment under test; EUT is exposed to an electric field by unit of an emission electrode, and an intensity of the electric field applied to the electronic equipment during a test is fluctuated by electric field fluctuating unit. Operating characteristics of the electronic equipment are tested by generating induction charging inside the electronic equipment by the fluctuation electric field during the test. As a result, it becomes possible to test malfunction caused by a discharge phenomenon generated inside the electronic equipment, which cannot be tested with a conventional ESD testing apparatus.

Abstract translation: 在测试仪器中，作为被测设备的电子设备; EUT通过发射电极单位暴露于电场，并且在测试期间施加到电子设备的电场强度由电场波动单元波动。 电子设备的工作特性通过在测试期间通过波动电场在电子设备内产生感应充电来测试。 结果，可以测试由常规ESD测试装置不能测试的电子设备内产生的放电现象引起的故障。

公开(公告)号：US20130066582A1

公开(公告)日：2013-03-14

申请号：US13228504

申请日：2011-09-09

Applicant: Georg Pelz ,  Thomas Nirmaier

Inventor： Georg Pelz ,  Thomas Nirmaier

IPC: G06F19/00 ,  G01R31/00

CPC classification number: G01R31/2601 ,  G01R31/2879 ,  G01R31/2894 ,  H01L22/14 ,  H01L22/20

Abstract: A method for determining test sets of operating parameter values for an electronic component, the method including: determining a first set of intermediate sets, each intermediate set containing a combination of a first number of operating parameters of the electronic component; determining a second set of reference sets, wherein the second set contains a union of sets, each set comprising all possible combinations of parameter values for the parameters of a respective intermediate set; selecting a third set with a second number of test sets out of a set of predefined sets, wherein each predefined set comprises a different combination of the parameter values for all parameters from the predefined parameter set, such that the second set is a subset of a union of a number of sets, each set comprising all possible combinations of the first number of parameter values for all parameters of a respective test set.

公开(公告)号：US20120299613A1

公开(公告)日：2012-11-29

申请号：US13368558

申请日：2012-02-08

Applicant: Naoto KAGUCHI ,  Masaaki IKEGAMI

Inventor： Naoto KAGUCHI ,  Masaaki IKEGAMI

IPC: G01R31/26

CPC classification number: G01R1/04 ,  G01R1/06777 ,  G01R31/129 ,  G01R31/2879 ,  G01R31/2886 ,  G01R31/2887 ,  H01L22/14

Abstract: A jig for use in a semiconductor test includes: a base on which a probe pin and an insulating material are placed, the insulating material surrounding the probe pin in plan view; and a stage arranged to face a surface of the base on which the probe pin and the insulating material are placed. The stage is capable of holding a test object on a surface of the stage facing the base. When the base and the stage move in a direction in which they go closer to each other while the test object is placed on the stage, the probe pin comes into contact with an electrode formed on the test object and the insulating material comes into contact with the test object.

Abstract translation: 用于半导体测试的夹具包括：放置探针和绝缘材料的基座，平面图中围绕探针的绝缘材料; 以及布置成面对放置探针和绝缘材料的基座的表面的台。 舞台能够将测试对象保持在面向基座的舞台的表面上。 当基座和台架沿测试对象放置在平台上时彼此靠近的方向移动时，探针与形成在测试对象上的电极接触，并且绝缘材料与 测试对象。

公开(公告)号：US20120130657A1

公开(公告)日：2012-05-24

申请号：US13170512

申请日：2011-06-28

Applicant: Martin ECKERT ,  Roland FRECH ,  Claudio SIVIERO ,  Jochen SUPPER ,  Otto A. TORREITER ,  Thomas-Michael WINKEL

Inventor： Martin ECKERT ,  Roland FRECH ,  Claudio SIVIERO ,  Jochen SUPPER ,  Otto A. TORREITER ,  Thomas-Michael WINKEL

IPC: G06F19/00

CPC classification number: G01R31/2851 ,  G01R31/2879 ,  G01R31/3004 ,  G01R31/3012 ,  G01R31/318575

Abstract: A method for determining power consumption of a power domain within an integrated circuit is presented. In a first step, a local power supply impedance profile (Z(f)) of this power domain is determined. Subsequently, a local time-resolved power supply voltage (U(t)) is measured while a well-defined periodic activity is executed in power domain. A set of time-domain measured voltage data (U(t)) is thus accumulated and transformed into the frequency domain to yield a voltage spectrum (U(f)). A current spectrum I(t) is calculated from this voltage profile (U(f)) by using the power supply impedance profile Z(f) of this power domain as I(t)=Ff−1{U(f)/Z(f)}. Finally, a time-resolved power consumption spectrum P(t) is determined from measured voltage spectrum U(t)) and calculated current spectrum (I(t)). This power consumption (P(t)) may be compared with a reference (Pref(t)) to verify whether power consumption within power domain matches expectations.

Abstract translation: 提出了一种用于确定集成电路内的功率域的功率消耗的方法。 在第一步中，确定该功率域的局部电源阻抗曲线（Z（f））。 随后，在功率域中执行明确定义的周期性活动的同时测量本地时间分辨的电源电压（U（t））。 因此，一组时域测量电压数据（U（t））被积累并变换到频域以产生电压谱（U（f））。 通过使用该功率域的电源阻抗曲线Z（f），I（t）= Ff-1 {U（f）/ Z），从该电压分布（U（f））计算电流频谱I （F）}。 最后，从测量的电压谱U（t））和计算出的当前频谱（I（t））确定时间分辨的功耗谱P（t）。 该功率消耗（P（t））可以与参考（Pref（t））进行比较，以验证功率域内的功耗是否符合预期。

公开(公告)号：US07902846B2

公开(公告)日：2011-03-08

申请号：US12684051

申请日：2010-01-07

Applicant: Steven C. Steps ,  Scott E. Lindsey ,  Kenneth W. Deboe ,  Donald P. Richmond, II ,  Alberto Calderon

Inventor： Steven C. Steps ,  Scott E. Lindsey ,  Kenneth W. Deboe ,  Donald P. Richmond, II ,  Alberto Calderon

IPC: G01R31/00

CPC classification number: G01R31/2875 ,  G01R1/0491 ,  G01R31/2856 ,  G01R31/2863 ,  G01R31/2865 ,  G01R31/2879 ,  G01R31/2889

Abstract: The invention relates to a tester apparatus of the kind including a portable supporting structure for removably holding and testing a substrate carrying a microelectronic circuit. An interface on the stationary structure is connected to the first interface when the portable structure is held by the stationary structure and is disconnected from the first interface when the portable supporting structure is removed from the stationary structure. An electrical tester is connected through the interfaces so that signals may be transmitted between the electrical tester and the microelectronic circuit to test the microelectronic circuit.

Abstract translation: 本发明涉及一种包括便携式支撑结构的测试器装置，该便携式支撑结构用于可移除地保持和测试承载微电子电路的基板。 当便携式结构由固定结构保持时，固定结构上的接口连接到第一接口，并且当便携式支撑结构从固定结构移除时与第一接口断开连接。 电气测试仪通过接口连接，以便信号可以在电气测试仪和微电子电路之间传输，以测试微电子电路。

公开(公告)号：US20100237879A1

公开(公告)日：2010-09-23

申请号：US12610270

申请日：2009-10-30

Applicant: WEI-PING WANG ,  Hsuan-Chung KO

Inventor： WEI-PING WANG ,  Hsuan-Chung KO

IPC: G01R27/28

CPC classification number: G01R31/2894 ,  G01R31/2879

Abstract: A method and apparatus for improving yield ratio of testing are disclosed. The method includes the following steps. First of all, devices are tested and electromagnetic interference is measured. Next, the test results are examined for whether the devices pass the test or not. Then, electromagnetic interference data are examined for whether the electromagnetic interference data are over a predetermined standard if the devices fail the test. The above-mentioned steps are performed again if the electromagnetic interference data are over a predetermined standard. The test is terminated if the devices still fail the test and the values of electromagnetic interference are still over a predetermined standard.

Abstract translation: 公开了一种用于提高测试屈服比的方法和装置。 该方法包括以下步骤。 首先，测试设备并测量电磁干扰。 接下来，检查测试结果是否通过测试。 然后，如果设备未通过测试，则检查电磁干扰数据是否超过预定标准。 如果电磁干扰数据超过预定标准，则再次执行上述步骤。 如果设备仍然测试失败并且电磁干扰值仍然超过预定标准，则测试终止。

公开(公告)号：US07652494B2

公开(公告)日：2010-01-26

申请号：US11753853

申请日：2007-05-25

Applicant: Daniel W. Dobberpuhl ,  Vincent R. von Kaenel

Inventor： Daniel W. Dobberpuhl ,  Vincent R. von Kaenel

IPC: G01R31/02

CPC classification number: G06F1/3203 ,  G01R31/2879 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.

Abstract translation: 在一个实施例中，集成电路包括至少一个测量单元，其被配置为产生指示集成电路可用于给定工作频率的电源电压的输出，以及耦合以接收输出的控制单元。 控制单元被配置为响应于输出而产生指示集成电路的所请求的电源电压的电压控制输出。 电压控制输出可以从集成电路输出供集成电路外部的电路使用，以产生用于集成电路的电源电压。

公开(公告)号：US07616417B2

公开(公告)日：2009-11-10

申请号：US11984360

申请日：2007-11-16

Applicant: Mitsuru Yoshida

Inventor： Mitsuru Yoshida

IPC: H02H3/20 ,  H02H9/04

CPC classification number: G01R31/2879 ,  H01L27/0266 ,  H01L2224/48091 ,  H01L2224/4813 ,  H03K17/08122 ,  H01L2924/00014

Abstract: In a semiconductor device including a semiconductor element to be protected having first and second electrodes, and a protection circuit coupled between the first and second electrodes, a switch circuit is inserted between the first and second electrodes in series to the protection circuit. The switch circuit is turned ON by such a voltage that turns ON the semiconductor element.

Abstract translation: 在包括具有第一和第二电极的要被保护的半导体元件的半导体器件中，以及耦合在第一和第二电极之间的保护电路，开关电路被插入到与保护电路串联的第一和第二电极之间。 开关电路通过导通半导体元件的电压而导通。

公开(公告)号：US07564256B2

公开(公告)日：2009-07-21

申请号：US12119834

申请日：2008-05-13

Applicant: Anne Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

Inventor： Anne Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

IPC: G01R31/26

CPC classification number: G01R31/2879 ,  G01R31/275 ,  G01R31/3008 ,  G01R31/31858

Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract translation: 测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。 该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。 此外，这些方法在应力测试期间提供更有效的应力。 该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。 通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

公开(公告)号：US07541829B1

公开(公告)日：2009-06-02

申请号：US12131487

申请日：2008-06-02

Applicant: Ronald J. Bolam ,  Terrance W. Kueper ,  David P. Paulsen ,  John E. Sheets, II

Inventor： Ronald J. Bolam ,  Terrance W. Kueper ,  David P. Paulsen ,  John E. Sheets, II

IPC: G01R31/00

CPC classification number: G01R31/2879

Abstract: A method for correcting of asymmetric shifts in threshold voltage of transistors caused by effects such as negative-bias temperature instability (NBTI) during burn-in. The method may include providing logic patterns to an integrated circuit, such that devices that were stressed during burn-in are relaxed, and devices that suffered less stress during burn-in are stressed.

Abstract translation: 用于校正由老化期间的负偏压温度不稳定性（NBTI）等效应引起的晶体管阈值电压的非对称偏移的方法。 该方法可以包括向集成电路提供逻辑图案，使得在老化期间受到压力的装置被放宽，并且在老化期间遭受较少应力的装置受到压力。