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    Display panel and electronic terminal
    31.
    发明授权
    Display panel and electronic terminal 有权

    公开(公告)号：US11960184B2

    公开(公告)日：2024-04-16

    申请号：US16972645

    申请日：2020-11-30

    Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

    Inventor： Wenqiang Yu ,  Guanghui Liu ,  Chao Wang

    IPC: G02F1/1362 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/137

    CPC classification number: G02F1/136286 ,  G02F1/133514 ,  G02F1/134309 ,  G02F1/133512 ,  G02F1/13439 ,  G02F1/137

    Abstract: The present invention discloses a display panel and an electronic terminal. The display panel includes a first display region and a second display region. The second display region includes a plurality of display subregions. Each of the plurality of display subregions includes a display portion and a light-transmitting portion. Each of the plurality of display subregions includes a switch control unit, a liquid crystal layer, a transparent electrode group, and a color filter layer. The liquid crystal layer is disposed in the display portion and the light-transmitting portion. The transparent electrode group is configured to control a deflection direction of liquid crystal molecules in the liquid crystal layer, which puts the light-transmitting portion in a light-transmitting state or an opaque state.

    MANUFACTURING METHOD FOR CMOS LTPS TFT SUBSTRATE
    36.
    发明申请
    MANUFACTURING METHOD FOR CMOS LTPS TFT SUBSTRATE 有权

    公开(公告)号：US20210091124A1

    公开(公告)日：2021-03-25

    申请号：US16309446

    申请日：2018-09-18

    Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

    Inventor： Lisheng Li ,  Guanghui Liu

    IPC: H01L27/12 ,  H01L29/10

    Abstract: The CMOS LTPS TFT substrate manufacturing method, by a semi-transparent mask, forms a second photoresist pattern having a second photoresist section above a second poly-Si active layer where P-type ion heavy doping is to be performed as protection. Then, N-type ions are effectively prevented from being implanted into the second poly-Si active layer's second source/drain contact region when conducting N-type ion heaving doping to the first poly-Si active layer. There is no need to compensate P-type ions during the subsequent P-type ion heavy doping to the second poly-Si active layer for forming the second source/drain contact region. The present invention therefore reduces the productivity loss in the P-type ion heaving doping process and, as N-type ion heaving doping does not affect the PMOS transistors, enhances the electrical convergence of the PMOS transistors. Damage to the film lattice structure by the ion implantation is also reduced, thereby increasing the device reliability.

    MANUFACTURING METHOD FOR AMORPHOUS SILICON TFT SUBSTRATE
    37.
    发明申请
    MANUFACTURING METHOD FOR AMORPHOUS SILICON TFT SUBSTRATE 审中-公开

    公开(公告)号：US20190355836A1

    公开(公告)日：2019-11-21

    申请号：US16313045

    申请日：2018-09-27

    Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

    Inventor： Guanghui Liu

    IPC: H01L29/66 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/768 ,  H01L21/285 ,  H01L27/12

    Abstract: A manufacturing method for amorphous silicon TFT substrate is provided. A first photoresist layer having three thicknesses is formed through a first exposure process. Through three etching processes and two ashing treatments, patterning four layers of amorphous silicon layer, N-type doped amorphous silicon layer, first transparent conductive layer, and the source drain metal layer is completed by the first photoresist layer. Patterning of passivation layer is then performed via a second exposure process. Finally, a second photoresist layer having a photoresist pattern with two thicknesses is formed through a third exposure process. Patterning the two layers of the second transparent conductive layer and the gate metal layer by the second photoresist layer by two etching processes and one ashing process. The present invention further saves a mask process compared with the existing 4mask process, realizing a 3mask fabrication process of the amorphous silicon TFT substrate.

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