公开(公告)号：US08286015B2

公开(公告)日：2012-10-09

申请号：US12477737

申请日：2009-06-03

Applicant: Sompong Paul Olarig ,  Chris Lionetti ,  Shiv Rajpal ,  Vladimir Sadovsky

Inventor： Sompong Paul Olarig ,  Chris Lionetti ,  Shiv Rajpal ,  Vladimir Sadovsky

IPC: G06F1/26

CPC classification number: G06F3/0625 ,  G06F1/3221 ,  G06F1/3268 ,  G06F3/0634 ,  G06F3/0689 ,  Y02D10/154

Abstract: A multi-device storage system can be arranged into power saving systems by placing one or more storage devices into a reduced power consuming state when the storage activity associated with the system is sufficiently reduced that an attendant decrease in throughput will not materially affect users of the storage system. Where data redundancy is provided for, a redundant storage device can be placed into the reduced power consuming state and its redundancy responsibilities can be transitioned to a partition of a larger storage device. Such transitions can be based on specific parameters, such as write cycles or latency, crossing thresholds, including upper and lower thresholds, they can also be based on pre-set times, or a combination thereof. Lifecycle information, including lifecycle information collected in real-time by storage devices on a block-by-block basis, can be utilized to obtain historical empirical data from which to select the pre-set times.

Abstract translation: 当与系统相关联的存储活动被充分地减少时，多个设备存储系统可以被布置到节能系统中，使得一个或多个存储设备进入降低的功耗状态，从而伴随着吞吐量的降低将不会实质上影响用户的 存储系统 在提供数据冗余的情况下，可以将冗余存储设备置于降低的功耗状态，并且其冗余责任可以转换到较大存储设备的分区。 这种转换可以基于特定参数，例如写入周期或延迟，交叉阈值，包括上限和下限阈值，它们也可以基于预设时间或其组合。 可以利用生命周期信息，包括逐个块地由存储设备实时收集的生命周期信息，以获得用于选择预设时间的历史经验数据。

公开(公告)号：US20100306544A1

公开(公告)日：2010-12-02

申请号：US12476890

申请日：2009-06-02

Applicant: Chris Lionetti ,  Sompong Paul Olarig

Inventor： Chris Lionetti ,  Sompong Paul Olarig

IPC: H04L9/32 ,  G06F12/14 ,  H04L9/08 ,  H04L9/00

CPC classification number: H04L9/083 ,  H04L2209/60 ,  H04L2209/805

Abstract: A secure container can comprise a security server, one or more container servers, and one or more sensors that can detect a breach of the physically secure computing environment provided by the container. A management server external to the container can be informed when the container is sealed and authorized and can subsequently provide a cryptographic key enabling the security server in the container to boot. Each container server can request and receive a cryptographic key from the security server enabling them to boot. If the container is breached, such keys can be withheld and any computing device that is powered off, or restarted, will be unable to complete a subsequent boot. If the container loses a support system and is degraded, so long as the security server does not lose power, it can provide the cryptographic keys to container servers restarted after the degradation is removed.

Abstract translation: 安全容器可以包括安全服务器，一个或多个容器服务器，以及一个或多个可以检测由容器提供的物理上安全的计算环境的传感器的传感器。 当容器被密封和授权时，可以通知容器外部的管理服务器，并且随后可以提供使容器中的安全服务器启动的加密密钥。 每个容器服务器可以从安全服务器请求和接收加密密钥，使其能够启动。 如果容器被破坏，则可以禁止这样的密钥，并且任何关闭或重新启动的计算设备将无法完成随后的启动。 如果容器丢失支持系统并且被降级，只要安全服务器不断电，它可以在去除劣化之后重新启动容器服务器的密码密钥。

公开(公告)号：US20100306484A1

公开(公告)日：2010-12-02

申请号：US12473225

申请日：2009-05-27

Applicant: Nathan Steven Obr ,  Sompong Paul Olarig ,  Shiv Rajpal

Inventor： Nathan Steven Obr ,  Sompong Paul Olarig ,  Shiv Rajpal

IPC: G06F12/00 ,  G06F12/16

CPC classification number: G06F3/061 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/068 ,  G06F12/0246 ,  G06F2212/7211

Abstract: A storage system can comprise storage devices having storage media with differing characteristics. An eviction handler can receive information regarding the state of storage media or of data stored thereon, as well as information regarding application or operating system usage, or expected usage, of data, or information regarding policy, including user-selected policy. Such information can be utilized by the eviction handler to optimize the use of the storage system by evicting data from storage media, including evicting data in order to perform maintenance on, or replace, such storage media, and evicting data to make room for other data, such as data copied to such storage media to facilitate pre-fetching or implement policy. The eviction handler can be implemented by any one or more of processes executing on a computing device, control circuitry of any one or more of the storage devices, or intermediate storage-centric devices.

Abstract translation: 存储系统可以包括具有不同特征的存储介质的存储设备。 驱逐处理者可以接收关于存储介质或其上存储的数据的状态的信息，以及关于包括用户选择的策略在内的关于策略的数据或有关策略的信息的应用或操作系统使用或预期使用的信息。 驱逐处理程序可以利用这种信息来优化存储系统的使用，方法是从存储介质中取出数据，包括逐出数据，以对这些存储介质进行维护或替换，以及驱逐数据为其他数据腾出空间 ，例如将数据复制到这样的存储介质以便于预取或实现策略。 驱逐处理程序可以由在计算设备上执行的任何一个或多个进程，任何一个或多个存储设备的控制电路或中间存储为中心的设备来实现。

公开(公告)号：US20100088470A1

公开(公告)日：2010-04-08

申请号：US12244454

申请日：2008-10-02

Applicant: Christopher Lionetti ,  Sompong Paul Olarig ,  Vladimir Sadovsky

Inventor： Christopher Lionetti ,  Sompong Paul Olarig ,  Vladimir Sadovsky

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F3/0632 ,  G06F3/0605 ,  G06F3/0616 ,  G06F3/0649 ,  G06F3/0689

Abstract: The method may query the disk drive for a size where size may be a total number of logical blocks on the disk drive. The drive may receive a size response where the size includes a total number of logical blocks on the disk drive. The number of usage blocks necessary to represent the number of logical blocks on the disk drive may then be determined and usage data may be stored in the usage blocks. The data may be stored in the buffer of the disk drive. The data may also be stored in the DDF of a RAID drive. The data may be used to permit incremental backups of disk drives by backing up only the blocks that are indicated as having been changed. In addition, information about the access to the drive may be collected and stored for later analysis.

Abstract translation: 该方法可以查询磁盘驱动器的大小，其大小可以是磁盘驱动器上逻辑块的总数。 驱动器可能会收到一个大小响应，其大小包括磁盘驱动器上的逻辑块总数。 然后可以确定表示磁盘驱动器上的逻辑块数量所需的使用块的数量，并且可以将使用数据存储在使用块中。 数据可能存储在磁盘驱动器的缓冲区中。 数据也可以存储在RAID驱动器的DDF中。 数据可用于通过仅备份指示为已更改的块来允许磁盘驱动器的增量备份。 此外，可以收集和存储有关访问驱动器的信息以供以后分析。

公开(公告)号：US07145914B2

公开(公告)日：2006-12-05

申请号：US10039190

申请日：2001-12-31

Applicant: Sompong Paul Olarig ,  Mark Lyndon Oelke ,  John E. Jenne

Inventor： Sompong Paul Olarig ,  Mark Lyndon Oelke ,  John E. Jenne

IPC: H04L12/56

CPC classification number: H04L12/5601 ,  H04L12/4625 ,  H04L29/06 ,  H04L47/10 ,  H04L47/2433 ,  H04L47/30 ,  H04L47/32 ,  H04L67/1097 ,  H04L69/18

Abstract: A heterogeneous and scalable bridge capable of translating a plurality of network protocols is adapted for coupling to a network switch fabric. The bridge uses at least one egress buffer interface and can perform port aggregation and bandwidth matching for various different port standards. The bridge is adapted for both networking and storage area networking protocols. A control unit is implemented with the bridge is able to identify control and flow information from different protocols and adapt them to the respective interface to which they are to be transmitted.

Abstract translation: 能够翻译多个网络协议的异构和可扩展的桥适合于耦合到网络交换结构。 该桥使用至少一个出口缓冲区接口，可以针对各种不同的端口标准执行端口聚合和带宽匹配。 该网桥适用于网络和存储区域网络协议。 实现一个控制单元，该桥接器能够识别来自不同协议的控制和流程信息，并将它们适应它们将被传输到的相应接口。

公开(公告)号：US07024510B2

公开(公告)日：2006-04-04

申请号：US10390476

申请日：2003-03-17

Applicant: Sompong Paul Olarig

Inventor： Sompong Paul Olarig

IPC: G06F13/36

CPC classification number: G06F13/4027 ,  G06F2213/0024

Abstract: In a computer system, a host-to-I/O bridge (e.g., a host-to-PCI-X bridge) includes core logic that interfaces with at least two host buses for coupling a central processing unit(s) and the bridge, and interfaces with at least two PCI-X buses for coupling at least two PCI-X devices and the bridge. The core logic includes at least two PCI-X configuration registers adapted to have bits set to partition the core logic for resource allocation. Embodiments of the present invention allow the system to program the logical bus zero to behave as a single logical bus zero or partition into two or more separate “bus zero” PCI-X buses with their own configuration resources. Partitioning allows performance and functional isolation and transparent I/O sharing.

Abstract translation: 在计算机系统中，主机到I / O桥（例如，主机到PCI-X桥）包括与至少两个主机总线接口的核心逻辑，用于耦合中央处理单元和桥 并与至少两个PCI-X总线接口，用于耦合至少两个PCI-X设备和桥接器。 核心逻辑包括至少两个PCI-X配置寄存器，其适于具有被设置为分配用于资源分配的核心逻辑的位。 本发明的实施例允许系统将逻辑总线零编程为表现为单个逻辑总线零或通过其自己的配置资源划分成两个或更多个单独的“总线零”PCI-X总线。 分区允许性能和功能隔离以及透明的I / O共享。

公开(公告)号：US06954209B2

公开(公告)日：2005-10-11

申请号：US10115551

申请日：2002-04-03

Applicant: Sompong Paul Olarig

Inventor： Sompong Paul Olarig

IPC: G06F12/10 ,  G09G5/36

CPC classification number: G06F12/1081

Abstract: A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of Accelerated Graphics Port (AGP) buses. Each of the plurality of AGP buses have the same logical bus number. The core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each AGP device connected to the plurality of AGP physical buses. Each of the plurality of AGP buses has its own read and write queues to provide transaction concurrency of AGP devices on different ones of the plurality of AGP buses when the transaction addresses are not the same or are M byte aligned. Upper and lower memory address range registers store upper and lower memory addresses associated with each AGP device. Whenever a transaction occurs, the transaction address is compared with the stored range of memory addresses. If a match between addresses is found then strong ordering is used. If no match is found then weak ordering may be used to improve transaction latency times. AGP device to AGP device transactions may occur without being starved by CPU host bus to AGP bus transactions.

Abstract translation: 计算机系统中的核心逻辑芯片组提供处理器主机和存储器总线与多个加速图形端口（AGP）总线之间的桥梁。 多个AGP总线中的每一个具有相同的逻辑总线号。 核心逻辑芯片组具有对连接到多个AGP物理总线的每个AGP设备具有请求（“REQ”）和Grant（“GNT”）信号线的仲裁器。 当交易地址不相同或是M字节对齐时，多个AGP总线中的每一个具有其自己的读取和写入队列以提供AGP设备在多个AGP总线上的不同的AGP总线上的事务并发。 上部和下部存储器地址范围寄存器存储与每个AGP设备相关联的上部和下部存储器地址。 每当事务发生时，将交易地址与存储的存储器地址范围进行比较。 如果发现地址之间的匹配，则使用强排序。 如果没有找到匹配，则可以使用弱排序来提高事务延迟时间。 AGP设备到AGP设备事务可能不会被CPU主机总线饿死到AGP总线事务。

公开(公告)号：US06792507B2

公开(公告)日：2004-09-14

申请号：US09738960

申请日：2000-12-14

Applicant: Lih-Sheng Chiou ,  Mike Witkowski ,  Hawkins Yao ,  Cheh-Suei Yang ,  Sompong Paul Olarig

Inventor： Lih-Sheng Chiou ,  Mike Witkowski ,  Hawkins Yao ,  Cheh-Suei Yang ,  Sompong Paul Olarig

IPC: G06F1208

CPC classification number: G06F12/0868 ,  G06F12/0813 ,  G06F2212/263 ,  G06F2212/284 ,  G06F2212/311 ,  G06F2212/312

Abstract: A cache system and method in accordance with the invention includes a cache near the target devices and another cache at the requesting host side so that the data traffic across the computer network is reduced. A cache updating and invalidation method are described.

Abstract translation: 根据本发明的缓存系统和方法包括目标设备附近的高速缓存和请求主机侧的另一个高速缓存，从而减少了计算机网络上的数据流量。 描述了缓存更新和无效方法。

公开(公告)号：US06530007B2

公开(公告)日：2003-03-04

申请号：US09902824

申请日：2001-07-10

Applicant: Sompong Paul Olarig ,  David J. Koenen ,  Chai S. Heng

Inventor： Sompong Paul Olarig ,  David J. Koenen ,  Chai S. Heng

IPC: G06F1300

CPC classification number: G06F13/1694

Abstract: A memory controller capable of supporting heterogeneous memory configurations enables seamless communications between a bus and memory modules having different characteristics. Thus, owners of computer systems need no longer replace entire memory arrays to take advantage of new memory modules; some memory modules may be upgraded to a new type while other memory modules of an older type remain. The memory controller receives memory requests from multiple processors and bus masters, identifies a memory module and memory access parameters for each request, accesses the memory and returns the resulting data (during a read request) or stores the data (during a write request). In some systems, the memory controller of the present invention is a two-tier memory controller system having a first memory controller coupled to the bus and to the second tier of memory controllers or RAM personality modules that translate between the first memory controller and a particular type of memory module. Typically, between the tiers a protocol is used which is representative of a typical clocked synchronous dynamic random access memory (SDRAM), although another protocol could be used. From the perspective of the processor bus or host bus coupled to the front end of the first memory controller, the entire memory controller system behaves as a single memory controller. From the perspective of memory, the back end of the RAM personality module is seen as a memory controller designed specifically to be configured for that memory type. Consequently, although the front end of the RAM personality module can be standardized across the system, compatible with the back end of the first memory controller, and in most embodiments of the present invention, the back end of the RAM personality module differs among the controller modules in the second tier, according to the variety of the memory modules in the memory system.

公开(公告)号：US6167476A

公开(公告)日：2000-12-26

申请号：US160280

申请日：1998-09-24

Applicant: Sompong Paul Olarig ,  Usha Rajagopalan ,  Ronald Timothy Horan

Inventor： Sompong Paul Olarig ,  Usha Rajagopalan ,  Ronald Timothy Horan

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: A computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus is provided with an AGP to AGP bridge connected to the standard AGP bus. The AGP to AGP bridge can accommodate two or more AGP-compatible devices that can be accessed through the standard AGP bus via the AGP to AGP bridge. A PCI to memory bridge is also provided within the AGP to AGP bridge so that PCI devices may be connected to the AGP to AGP bridge. The AGP to AGP bridge is fitted with an overall flow control logic that controls the transfer of data to or from the various AGP devices and the standard AGP bus that is connected to the core logic of the computer system. The AGP to AGP Bridge can utilize a standard 32-bit AGP bus as well as (two) dual 32-bit buses to enhance bandwidth. In an alternate embodiment of the invention, the dual 32-bit buses can be combined to form a single 64-bit bus to increase the available bandwidth. Alternate embodiments of the AGP to AGP Bridge can accommodate the single 64-bit AGP bus for increased performance. Another alternate embodiment can accommodate peer-to-peer transfer of data between AGP busses on the bridge.

Abstract translation: 具有至少一个中央处理单元，系统存储器和能够接受AGP总线的核心逻辑的计算机系统具有AGP连接到标准AGP总线的AGP桥。 AGP到AGP桥可以容纳两个或更多AGP兼容的设备，可以通过AGP到AGP桥通过标准AGP总线访问。 在AGP到AGP桥接器之间还提供PCI到存储器桥，使得PCI设备可以连接到AGP到AGP桥。 AGP到AGP桥配有一个总体流量控制逻辑，用于控制数据传输到或来自各种AGP设备和连接到计算机系统的核心逻辑的标准AGP总线。 AGP到AGP Bridge可以使用标准的32位AGP总线以及（两个）双32位总线来增强带宽。 在本发明的替代实施例中，双32位总线可以组合以形成单个64位总线，以增加可用带宽。 AGP到AGP Bridge的替代实施例可以容纳单个64位AGP总线，以提高性能。 另一替代实施例可以适应桥上AGP总线之间的数据对等传输。