公开(公告)号：US09984931B2

公开(公告)日：2018-05-29

申请号：US15260952

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo Han ,  Kwang-Yong Yang ,  Jinwook Lee ,  Kyungyub Jeon ,  Haegeon Jung ,  Dohyoung Kim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/306

CPC classification number: H01L21/823431 ,  H01L21/30604 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.

公开(公告)号：US09941174B2

公开(公告)日：2018-04-10

申请号：US15007711

申请日：2016-01-27

Applicant: Samsung Electronics Co., Ltd

Inventor： Kyungin Choi ,  Ah-Young Cheon ,  Kwang-Yong Yang ,  Myungil Kang ,  Dohyoung Kim ,  YoonHae Kim

IPC: H01L31/0312 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66545

Abstract: Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.

公开(公告)号：US09785465B2

公开(公告)日：2017-10-10

申请号：US14722464

申请日：2015-05-27

Applicant: Samsung Electronics Co., Ltd

Inventor： Joohwan Kim ,  Dohyoung Kim ,  Hyunjin Park

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4856 ,  G06F9/5088 ,  Y02D10/32

Abstract: Provided is a method for task migration in an electronic device. The method includes: assigning a task with a specific function to a first group among groups formed according to a preset criterion; assigning the first group to one of first processing units functionally connected to the electronic device; and migrating, when the first group matches preset criteria of second processing units functionally connected to the electronic device, the first group to one of the second processing units. Based on this, it is possible to create various other embodiments.

公开(公告)号：US20170168872A1

公开(公告)日：2017-06-15

申请号：US15115641

申请日：2015-01-29

Applicant: Samsung Electronics Co., Ltd

Inventor： Dohyoung Kim ,  Joohwan Kim ,  Hyunjin Park ,  Changhwan Youn ,  Donghee Han

IPC: G06F9/48 ,  G06F9/50

Abstract: Provided is a task scheduling method. The method may include: assigning a task to one of first processing units functionally connected to an electronic device; and migrating, at least partially on the basis of a performance control condition related to the task, the task to one of second processing units for processing.

公开(公告)号：US09536983B2

公开(公告)日：2017-01-03

申请号：US14970710

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Young Lee ,  Dohyoung Kim ,  Johnsoo Kim ,  Heungsik Park ,  Hongsik Shin ,  Younghun Choi

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming a gate electrode on a substrate, forming a first spacer on a sidewall of the gate electrode, forming a second spacer on the first spacer, and forming a capping pattern on top surfaces of the gate electrode, the first spacer and the second spacer. An outer sidewall of the second spacer is vertically aligned with a sidewall of the capping pattern.

Abstract translation: 形成半导体器件的方法包括在衬底上形成栅电极，在栅电极的侧壁上形成第一间隔物，在第一间隔物上形成第二间隔物，并在栅电极的顶表面上形成封盖图案， 第一间隔物和第二间隔物。 第二间隔件的外侧壁与封盖图案的侧壁垂直对齐。