公开(公告)号：US10446587B2

公开(公告)日：2019-10-15

申请号：US15594325

申请日：2017-05-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ji-Sun Kim ,  Ji-Hyun Kim ,  Shin-Il Choi ,  Yeong-Keun Kwon

IPC: H01L27/12

Abstract: A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.

公开(公告)号：US10134352B2

公开(公告)日：2018-11-20

申请号：US15383686

申请日：2016-12-19

Applicant: Samsung Display Co., Ltd.

Inventor： Jae-Keun Lim ,  Ji-Sun Kim ,  Kyoung-Ju Shin ,  Chong-Chul Chai ,  Jong-Hee Kim

IPC: G09G3/36

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

公开(公告)号：US10102807B2

公开(公告)日：2018-10-16

申请号：US15157350

申请日：2016-05-17

Applicant: Samsung Display Co., Ltd.

Inventor： Jae Keun Lim ,  Jong Hee Kim ,  Ji-Sun Kim ,  Young Wan Seo ,  Chong Chul Chai

IPC: G09G5/00 ,  G09G3/3283 ,  G09G3/3233

Abstract: There is provided a display device including a display including a first pixel connected to a first data line and a second pixel connected to a second data line, a data signal generator configured to generate an output signal, and a signal divider configured to divide the output signal, to generate a first data signal and a second data signal, and to apply the first data signal and the second data signal to the first data line and the second data line, respectively, wherein the data signal generator is configured to generate the output signal based on a coupling effect of a first parasitic capacitor formed between the first data line and the second data line and a coupling effect of a parasitic capacitor of a data line formed by the first data line and second data line.

公开(公告)号：US09666613B2

公开(公告)日：2017-05-30

申请号：US14247818

申请日：2014-04-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ji-Sun Kim ,  Ji-Hyun Kim ,  Shin-Il Choi ,  Yeong-Keun Kwon

IPC: H01L27/12

CPC classification number: H01L27/1244 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259

Abstract: A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.

公开(公告)号：US09293093B2

公开(公告)日：2016-03-22

申请号：US14231001

申请日：2014-03-31

Applicant: Samsung Display Co., LTD.

Inventor： Jong-Hee Kim ,  Yeong-Keun Kwon ,  Ji-Sun Kim ,  Jae-Keun Lim ,  Chong-Chul Chai

IPC: G09G3/36

CPC classification number: G09G3/3611 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/08

Abstract: A gate driver circuit includes an N-th stage (‘N’ is a natural number) The N-th stage (‘N’ is a natural number) includes a pull-up part configured to output an N-th gate signal using a first clock signal in response to a node signal of the control node, a carry part configured to output an N-th carry signal using the first clock signal in response to the node signal of the control node, an first output part connected to an n-th gate line and configured to output an n-th gate signal using the N-th gate signal in response to a second clock signal having a period shorter than the first clock signal (‘n’ is a natural number), and a second output part connected to an (n+1)-th gate line and configured to output an (n+1)-th gate signal using the N-th gate signal in response to an second inversion clock signal having a phase opposite to the second clock signal.

Abstract translation: 栅极驱动器电路包括第N级（“N”是自然数）第N级（“N”是自然数）包括被配置为使用第n级输出第N门信号的上拉部分 响应于所述控制节点的节点信号的第一时钟信号，被配置为响应于所述控制节点的节点信号而使用所述第一时钟信号输出第N进位信号的进位部分，连接到所述控制节点的第一输出部分 并且被配置为响应于具有比第一时钟信号（'n'是自然数）短的周期的第二时钟信号，使用第N个门信号输出第n个门信号，第二 输出部分连接到第（n + 1）栅极线，并被配置为响应于具有与第二栅极相反相位的第二反相时钟信号，使用第N栅极信号输出第（n + 1）栅极信号 时钟信号。

公开(公告)号：US20150042638A1

公开(公告)日：2015-02-12

申请号：US14456976

申请日：2014-08-11

Applicant: SAMSUNG DISPLAY CO., LTD. ,  Industry-University Cooperation Foundation Hanyang-University

Inventor： Oh-Kyong Kwon ,  Yeong-Keun Kwon ,  Jong-Hee Kim ,  Ji-Sun Kim ,  Jae-Keun Lim ,  Chong-Chul Chai

IPC: G09G3/36

CPC classification number: G09G3/3225 ,  G09G3/3266 ,  G09G2310/0264 ,  G09G2310/0289 ,  G09G2310/08 ,  G11C19/28

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract translation: 舞台电路包括第一驱动器，第二驱动器，第一输出单元，第二输出单元和控制器。 第一驱动器根据第一电源，第三电源，开始信号或前一级输入到第一输入端的进位信号来控制第一和第二节点的电压，以及提供给第二输入端的时钟信号 终奌站。 第二驱动器根据第一电源，第三电源，第一输入端和第一和第二节点的电压来控制第三和第四节点的电压。 第一输出单元根据第一电源，第二输入端和第三和第四节点的电压将输入信号输出到第一输出端。 第二输出单元根据第二电源，第二输入端和第三和第四节点的电压向第二输出端输出扫描信号。 控制器电耦合到第一输出端子和第二驱动器。

公开(公告)号：US20150042383A1

公开(公告)日：2015-02-12

申请号：US14456995

申请日：2014-08-11

Applicant: Samsung Display Co., Ltd. ,  Industry-University Cooperation Foundation Hanyang-University

Inventor： Oh-Kyong Kwon ,  Yeong-Keun Kwon ,  Jong-Hee Kim ,  Ji-Sun Kim ,  Jae-Keun Lim ,  Chong-Chul Chai

IPC: G09G3/14 ,  H03K17/687

CPC classification number: H03K17/687 ,  G09G3/3266 ,  G09G2310/0286 ,  G09G2310/06 ,  G11C19/184 ,  G11C19/28

Abstract: A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.

Abstract translation: 舞台电路包括第一驱动器，第二驱动器，第一输出单元和第二输出单元。 第一驱动器根据第一电源，提供给第一输入端的前一级的起始信号或进位信号，提供给第二输入端的第一时钟信号和第二驱动器控制第一和第二节点的电压， 提供给第三输入端的时钟信号。 第二驱动器根据第一电源控制第三节点的电压，提供给第一输入端的先前级的起始信号或进位信号，提供给第四输入端的下一级的进位信号， 和第二节点的电压。

公开(公告)号：US08816728B2

公开(公告)日：2014-08-26

申请号：US14057354

申请日：2013-10-18

Applicant: Samsung Display Co., Ltd.

Inventor： Soo-Wan Yoon ,  Yeong-Keun Kwon ,  Ji-Sun Kim ,  Young-Soo Yoon ,  Chong-Chui Chai

IPC: H03K3/00

CPC classification number: H03K3/012 ,  G09G3/3674 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/184 ,  G11C19/28

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.

Abstract translation: 栅极驱动电路包括上拉控制部分，上拉部分，携带部分，第一下拉部分和第二下拉部分。 上拉控制部分将来自前一级的进位信号应用于第一节点。 上拉部分基于时钟信号输出第N个栅极输出信号。 进位部分响应于施加到第一节点的信号，基于时钟信号输出第N个进位信号。 第一下拉部分包括彼此串联连接的多个晶体管。 第一下拉部分响应于下一级的进位信号将第一节点处的信号拉低至第二截止电压。 第二下拉部分响应于下一级的进位信号将第N栅极输出信号拉低至第一关断电压。

公开(公告)号：US20140043066A1

公开(公告)日：2014-02-13

申请号：US14057354

申请日：2013-10-18

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Soo-Wan Yoon ,  Yeong-Keun Kwon ,  Ji-Sun Kim ,  Young-Soo Yoon ,  Chong-Chul Chai

IPC: H03K3/012

CPC classification number: H03K3/012 ,  G09G3/3674 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/184 ,  G11C19/28

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.

Abstract translation: 栅极驱动电路包括上拉控制部分，上拉部分，携带部分，第一下拉部分和第二下拉部分。 上拉控制部分将来自前一级的进位信号应用于第一节点。 上拉部分基于时钟信号输出第N个栅极输出信号。 进位部分响应于施加到第一节点的信号，基于时钟信号输出第N个进位信号。 第一下拉部分包括彼此串联连接的多个晶体管。 第一下拉部分响应于下一级的进位信号将第一节点处的信号拉低至第二截止电压。 第二下拉部分响应于下一级的进位信号将第N栅极输出信号拉低至第一关断电压。