Abstract:
A method of manufacturing a touch screen panel, including forming first and second conductive layers and an organic insulating layer on a substrate; forming a first organic insulating pattern having a first thickness and a second organic insulating pattern having a second thickness, the second thickness being larger than the first thickness; forming first and second conductive patterns; exposing a part of the second conductive pattern to form a third organic insulating pattern having a thickness smaller than the second thickness; removing the exposed second conductive pattern; forming an organic insulating capping layer surrounding the first and second conductive patterns positioned under the third organic insulating pattern; and forming a third conductive layer on the first conductive pattern and the organic insulating capping layer, the first conductive pattern being exposed, and then forming a connection pattern electrically connected with the exposed first conductive pattern using a second mask.
Abstract:
A photoresist composition includes an acid-labile polymer that is decomposable by reaction with an acid, a photoacid generator, an organic base having a pKa value of 9 or less and a solvent. Based on 100 parts by weight of the acid-labile polymer, the photoacid generator is about 1 to about 30 parts by weight, and the organic base is about 0.1 to about 5 parts by weight. The solvent is about 50 to about 90 wt % based on the total weight of the composition.
Abstract:
A method of manufacturing a pattern includes forming a pattern material layer on a substrate, forming a protective layer on the pattern material layer, forming a resist layer on the protective layer, selectively exposing the resist layer to light, and developing the selectively exposed resist layer.
Abstract:
A thin film transistor (TFT) array panel and a manufacturing method thereof are disclosed. A contact hole may be formed to expose a pad disposed on a substrate of the TFT array panel. A first layer of a connecting member is formed with the same layer as a first field generating electrode and is disposed in the contact hole. A second passivation layer is disposed in the TFT array panel, but is removed at a region where the contact hole is formed and portions of the second passivation layer that cover the first layer of the connecting member. A second layer of the connecting member is formed on the first layer of the connecting member.
Abstract:
Instead of forming contact holes the same way in both the non-image forming peripheral area (PA) and the image forming display area of a thin film transistor array panel, contact holes in the DA are formed to be substantially smaller than those in the PA for thereby improving an aperture ratio of the corresponding display device. In an exemplary embodiment, an inorganic gate insulating layer is not etched in the DA and only an inorganic first passivation layer among inorganic insulating layers positioned in the DA is etched to allow communication between the drain electrode and the corresponding field generating electrode. On the other hand, in the peripheral area, plural inorganic insulating layers such as the gate insulating layer, the first passivation layer, and the second passivation layer positioned on the gate wire and the data wire are simultaneously etched to form second contact holes and third contact holes exposing respective gate pads and data pads.
Abstract:
A display apparatus includes a first substrate, a second substrate disposed on the first substrate, and a controllable layer disposed between the first and second substrates. The first substrate includes a pixel. The pixel includes a display region and a non-display region. The first substrate further includes: a transistor disposed in the non-display region; a protection layer disposed on and covering the transistor; a first electrode disposed on the protection layer; and a second electrode disposed on the first electrode, the second electrode being insulated from the first electrode and including a slit disposed in the display region. One of the first electrode and the second electrode is electrically connected to the transistor via a contact hole extending through the protection layer. The other of the first electrode and the second electrode is configured to receive a common voltage. The contact hole and the slit do not overlap one another.