公开(公告)号：US20210320059A1

公开(公告)日：2021-10-14

申请号：US16846591

申请日：2020-04-13

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  John Jianhong ZHU ,  Lixin GE

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/528

Abstract: Certain aspects of the present disclosure generally relate to a hybrid back-end-of-line (BEOL) dielectric for a high capacitance density metal-oxide-metal (MOM) capacitor, especially in lower BEOL layers. One example semiconductor device includes an active layer and a first metal layer disposed above the active layer. The first metal layer generally includes: a first electrode; a second electrode, wherein the first and second electrodes have interdigitated fingers; a first dielectric material disposed at least partially between at least two adjacent fingers of the first and second electrodes; and a second dielectric material, wherein the second dielectric material is different from the first dielectric material and wherein the first electrode, the second electrode, and the first dielectric material compose a portion of a metal-oxide-metal (MOM) capacitor.

公开(公告)号：US20210057404A1

公开(公告)日：2021-02-25

申请号：US16990418

申请日：2020-08-11

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Xiaoju YU ,  Ye LU

IPC: H01L27/01 ,  H01L27/02 ,  H01L23/60

Abstract: Disclosed are devices and methods for on-die electrostatic discharge (ESD) protection in an electronic device. Aspects disclosed include an electronic device including a protected circuit disposed within a die having a first port and a second port. A first inductor is also disposed within the die and is electrically coupled to the first port. A second inductor is also disposed within the die and electrically coupled to the second port. The first inductor and the second inductor are routed in close proximity and are configured so the first inductor is out of phase with the second inductor.

公开(公告)号：US20210036168A1

公开(公告)日：2021-02-04

申请号：US16674002

申请日：2019-11-05

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Gang LIU ,  Zhongze WANG

IPC: H01L29/94 ,  H01L29/66 ,  H01L27/08

Abstract: Aspects generally relate to a complimentary MOS capacitor with improved linearity. A complimentary MOS capacitor includes an n-type MOS capacitor and a p-type MOS capacitor coupled in parallel. The p-type MOS capacitor biased to an opposite voltage polarity of the n-type MOS capacitor.

公开(公告)号：US20200234999A1

公开(公告)日：2020-07-23

申请号：US16250098

申请日：2019-01-17

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Peijie FENG ,  Chenjie TANG

IPC: H01L21/764 ,  H01L27/092 ,  H01L21/8238

Abstract: Certain aspects of the present disclosure provide a transistor device, such as a fin field-effect transistor (finFET) device, and techniques for fabrication thereof. One example transistor device generally includes one or more semiconductor channel regions and a metal region disposed above the one or more semiconductor channel regions. The metal region has one or more gaps (e.g., air gaps) disposed therein.

公开(公告)号：US20200083158A1

公开(公告)日：2020-03-12

申请号：US16126406

申请日：2018-09-10

Applicant: QUALCOMM Incorporated

Inventor： Chao SONG ,  Ye LU ,  Haitao CHENG

IPC: H01L23/522 ,  H01L27/01

Abstract: Certain aspects of the present disclosure provide an integrated circuit (IC) that includes at least one of a via-based vertical capacitor structure or a via-based vertical resistor structure. The IC includes a substrate oriented in a horizontal plane, electrically conductive layers disposed above the substrate, and electrically insulative layers disposed above the substrate and interposed between the plurality of electrically conductive layers. At least one of the vertical capacitor structure or the vertical resistor structure is disposed in the electrically conductive layers and the electrically insulative layers.

公开(公告)号：US20190393359A1

公开(公告)日：2019-12-26

申请号：US16119914

申请日：2018-08-31

Applicant: QUALCOMM Incorporated

Inventor： Chuan-Hsing CHEN ,  Chuan-cheng CHENG ,  Yun YUE ,  Ye LU

IPC: H01L29/93 ,  H01L29/66 ,  H01L21/225

Abstract: A metal oxide semiconductor (MOS) varactor includes a first diffusion region of a first polarity and a second diffusion region of the first polarity on a semiconductor substrate. The MOS varactor further includes a channel between the first diffusion region and the second diffusion region on the semiconductor substrate. The channel has a surface dopant concentration less than 4 e1017.

公开(公告)号：US20190386092A1

公开(公告)日：2019-12-19

申请号：US16009976

申请日：2018-06-15

Applicant: QUALCOMM Incorporated

Inventor： Haitao CHENG ,  Ye LU ,  Chao SONG

IPC: H01L49/02

Abstract: A capacitor has reduced misalignment in the interconnect layers and lower capacitance variance. The capacitor includes a first endcap having a first section and a second section orthogonal to the first section. The capacitor includes a first set of conductive fingers orthogonally coupled to the first section. The capacitor includes a third set of conductive fingers orthogonally coupled to the second section of the endcap and a second endcap parallel to the first section of the endcap. The capacitor includes a second set of conductive fingers orthogonally coupled to a second endcap and interdigitated with the first set of conductive fingers at a first interconnect layer. The capacitor includes a third endcap parallel to the second section of the first endcap and a fourth set of conductive fingers orthogonally coupled to the third endcap and interdigitated with the third set of conductive fingers at the first interconnect layer.

公开(公告)号：US20190305077A1

公开(公告)日：2019-10-03

申请号：US15937097

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Peijie FENG ,  Junjing BAO ,  Ye LU ,  Giridhar NALLAPATI

IPC: H01L49/02 ,  H01L23/522

Abstract: A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers. A first set of vias electrically couples the first conductive fingers to the fifth conductive fingers.