公开(公告)号：US20150109293A1

公开(公告)日：2015-04-23

申请号：US14061506

申请日：2013-10-23

Applicant: QUALCOMM Incorporated

Inventor： Tao Wang ,  Andrew Evan Gruber ,  Shambhoo Khandelwal

IPC: G06T15/40 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T15/405 ,  G06T1/60 ,  G06T15/005

Abstract: This disclosure describes techniques for performing hierarchical z-culling in a graphics processing system. In some examples, the techniques for performing hierarchical z-culling may involve selectively merging partially-covered source tiles for a tile location into a fully-covered merged source tile based on whether conservative farthest z-values for the partially-covered source tiles are nearer than a culling z-value for the tile location, and using a conservative farthest z-value associated with the fully-covered merged source tile to update the culling z-value for the tile location. In further examples, the techniques for performing hierarchical z-culling may use a cache unit that is not associated with an underlying memory to store conservative farthest z-values and coverage masks for merged source tiles. The capacity of the cache unit may be smaller than the size of cache needed to store merged source tile data for all of the tile locations in a render target.

Abstract translation: 本公开描述了在图形处理系统中执行分层z剔除的技术。 在一些示例中，用于执行分层z剔除的技术可以包括基于对于部分覆盖的源平铺的保守最远的z值是否更接近而选择性地将用于瓦片位置的部分覆盖的源瓦片合并到完全覆盖的合并源瓦片中 比用于瓦片位置的剔除z值，以及使用与完全覆盖的合并源平铺相关联的保守最远的z值来更新瓦片位置的剔除z值。 在另外的示例中，用于执行分层z剔除的技术可以使用与底层存储器不相关联的高速缓存单元来存储用于合并的源瓦片的保守最远的z值和覆盖掩码。 高速缓存单元的容量可以小于存储渲染目标中的所有瓦片位置的合并的源瓦片数据所需的高速缓存的大小。

公开(公告)号：US11600002B2

公开(公告)日：2023-03-07

申请号：US16892096

申请日：2020-06-03

Applicant: QUALCOMM Incorporated

Inventor： Jian Liang ,  Andrew Evan Gruber ,  Tao Wang ,  Srihari Babu Alla ,  Kalyan Kumar Bhiravabhatla ,  Jonnala Gadda Nagendra Kumar ,  William Licea-Kane ,  Fredrick Alan Hickman

IPC: G06T7/11 ,  G06T1/60 ,  G06T1/20 ,  G06T7/136 ,  G06T5/40

Abstract: Methods, systems, and devices for graphics processing are described. A device may receive an image including a set of pixels. The device may render a first subset of pixels in each bin of a set of bins during a first rendering pass, and defer rendering a second subset of pixels and a third subset of pixels in each bin of the set of bins during the first rendering pass. The second subset of pixels may include edge pixels and the third subset of pixels may be between the first subset of pixels and the second subset of pixels. The device may render the second subset of pixels and the third subset of pixels in each bin of the set of bins during a second rendering pass based on rendering the first subset of pixels. The device may then output the image based on the first and second rendering pass.

公开(公告)号：US20170249771A1

公开(公告)日：2017-08-31

申请号：US15054717

申请日：2016-02-26

Applicant: QUALCOMM Incorporated

Inventor： Juraj Obert ,  Tao Wang ,  Vineet Goel

IPC: G06T15/00 ,  G06T15/06

CPC classification number: G06T15/005 ,  G06T15/06 ,  G06T2200/28 ,  G06T2210/21

Abstract: A render output unit running on at least one processor may receive a source pixel value to be written to a pixel location in a render target, wherein the source pixel value is associated with a source node in a hierarchical structure. The render output unit may receive a destination pixel value of the pixel location in the render target, wherein the destination pixel value is associated with a destination node in the hierarchical structure. The render output unit may determine a lowest common ancestor node of the source node and the destination node in the hierarchical structure. The render output unit may output a resulting pixel value associated with the lowest common ancestor node of the source node and the destination node to the pixel location in the render target.

公开(公告)号：US20170084043A1

公开(公告)日：2017-03-23

申请号：US14862532

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Shambhoo Khandelwal ,  Yang Xia ,  Xuefeng Tang ,  Jian Liang ,  Tao Wang ,  Andrew Evan Gruber ,  Eric Demers

IPC: G06T7/20 ,  G06T1/20 ,  G06T15/80 ,  G06T1/60

CPC classification number: G06T7/20 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/80 ,  G06T2200/04 ,  G06T2200/28

Abstract: A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.

公开(公告)号：US20150235340A1

公开(公告)日：2015-08-20

申请号：US14454394

申请日：2014-08-07

Applicant: QUALCOMM Incorporated

Inventor： Ouns Mouri ,  Vineet Goel ,  Tao Wang

IPC: G06T1/20 ,  G06T17/10 ,  G09G5/18

CPC classification number: G06T1/20 ,  G06T11/40 ,  G06T17/10 ,  G09G5/18 ,  G09G2310/08

Abstract: This disclosure describes a method for performing conservative rasterization in a processor comprising determining vertices of a primitive, defining edges of the primitive by determining a set of edge equations based on the determined vertices, wherein the edge equations are based on an edge shifting parameter plus an offset, determining pixels that touch the edges of the primitive using the determined edge equations, and rasterizing the primitive using the determined pixels.

Abstract translation: 本公开描述了一种用于在处理器中执行保守光栅化的方法，包括通过基于所确定的顶点确定一组边缘方程来确定原语的边缘来定义基元的边缘，其中边缘方程基于边缘移位参数加上 使用所确定的边缘方程来确定触摸图元的边缘的像素，以及使用所确定的像素来对原图进行光栅化。