公开(公告)号：US12212074B2

公开(公告)日：2025-01-28

申请号：US17651832

申请日：2022-02-21

Applicant: NXP B.V.

Inventor： Jan Willem Bergman ,  Mustafa Acar ,  Antonius Hendrikus Jozef Kamphuis ,  Dominicus Martinus WilHelmus Leenaerts ,  Rajesh Mandamparambil ,  Paul Mattheijssen

IPC: H01L23/66 ,  H01Q3/34

Abstract: An integrated circuit comprising a package, phased antenna array and die. The die comprises a plurality of unit cells, wherein each unit cell is divided into quadrants. Each quadrant comprises a receiver terminal located on a first axis, and a transmitter terminal located on a second axis, wherein the first axis is orthogonal to the second axis, and there is mirror symmetry between the nearest neighbour quadrants in the unit cell. The package comprises a plurality of pairs of feed lines, each pair of feed lines comprising a receiver feed line and a transmitter feed line. The receiver feed line is connected to one of the receiver terminals and the transmitter feed line is connected to the transmitter terminal in the same die quadrant. The receiver feed line is orthogonal to the transmitter feed line. Each antenna element is coupled to a respective pair of feed lines.

公开(公告)号：US20240237316A9

公开(公告)日：2024-07-11

申请号：US18048495

申请日：2022-10-21

Applicant: NXP B.V.

Inventor： Philipp Franz Freidl ,  Mustafa Acar ,  Antonius Hendrikus Jozef Kamphuis ,  Erik Daniel Björk ,  Konstantinos Giannakidis ,  Jan Willem Bergman ,  Rajesh Mandamparambil ,  Paul Mattheijssen

IPC: H05K9/00 ,  H01L23/552

CPC classification number: H05K9/0032 ,  H01L23/552 ,  H05K9/0088

Abstract: One example discloses an on-chip shielded device, including: a planar structure including a substrate and a passivation layer; an electrical component formed within the substrate and coupled to an input signal path and an output signal path; a first shielding element positioned above the electrical component and the passivation layer; and a second shielding element positioned above the electrical component, the passivation layer and the first shielding element.

公开(公告)号：US20240106101A1

公开(公告)日：2024-03-28

申请号：US18459815

申请日：2023-09-01

Applicant: NXP B.V.

Inventor： Xin Yang ,  Mustafa Acar ,  Zhe Chen ,  Dominicus MARTINUS WILHELMUS Leenaerts

IPC: H01P5/12

CPC classification number: H01P5/12

Abstract: A circuit comprising: a common terminal, first terminal and second terminal, wherein the common terminal is coupled to a first and second circuit branch at a branch node; wherein the first/second circuit branches include a respective first/second quarter wavelength transmission line having a first end coupled to the branch node and a second end respectively coupled to the first/second terminal; wherein the first and second terminals are coupled together via a branch-interconnection arrangement; wherein the circuit comprises: a first switched arrangement comprising a first switch having a first and second switch-terminal, wherein the first switch-terminal is coupled to the common terminal, and wherein a first resistor and a first capacitor are arranged in parallel and coupled between the second switch-terminal and a reference terminal; and a second switched arrangement coupled to the first terminal, wherein the first quarter wavelength transmission line is coupled between the first and second switched arrangements.

公开(公告)号：US20230402410A1

公开(公告)日：2023-12-14

申请号：US18315515

申请日：2023-05-11

Applicant: NXP B.V.

Inventor： Mustafa Acar ,  Paul Mattheijssen ,  Philipp Franz Freidl ,  Rajesh Mandamparambil ,  Jan Willem Bergman

IPC: H01L23/66 ,  H01L25/16

CPC classification number: H01L23/66 ,  H01L25/16 ,  H01L2223/6644

Abstract: An RF package assembly includes a stacked package-on-package arrangement of a first substrate and a second substrate. Each of the first and second substrates include RF signal pads and ground pads. An interface region between the stacked substrates couples the RF signal pads and ground pads of the first substrate to corresponding pads of the second substrate. The interface region includes galvanic connection regions providing a galvanic connection between the each of the first substrate ground pads and each of the corresponding second substrate ground pads. The interface region includes dielectric regions between each of the first substrate RF signal pads and the corresponding second substrate RF signal pads so that RF signals transmitted between the two substrates are capacitively coupled.

公开(公告)号：US20230290737A1

公开(公告)日：2023-09-14

申请号：US17694330

申请日：2022-03-14

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Mustafa Acar ,  Philipp Franz Freidl ,  Rajesh Mandamparambil ,  Jan Willem Bergman

IPC: H01L23/552 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L23/481 ,  H01L23/3128 ,  H01L21/56

Abstract: A flip chip device includes a substrate, an integrated circuit device, a mold compound, and a via. The substrate has a top side and a bottom side. The integrated circuit device is affixed to the bottom side of the substrate. The mold compound is affixed to the bottom side of the substrate. The via is affixed to the bottom side of the substrate. The via passes through the mold compound and is exposed at a bottom side of the mold compound. The via is coupled to a terminal of the integrated circuit device.

公开(公告)号：US20220384943A1

公开(公告)日：2022-12-01

申请号：US17664089

申请日：2022-05-19

Applicant: NXP B.V.

Inventor： Mustafa Acar ,  Philipp Franz Freidl ,  Antonius Hendrikus Jozef Kamphuis ,  Jan Willem Bergman ,  Rajesh Mandamparambil

IPC: H01Q1/48

Abstract: A semiconductor device may include an antenna array and a grounding assembly configured to at least partially electrically shield the antenna array. The grounding assembly may include a first grounding layer comprising a first plurality of openings and a second grounding layer comprising a second plurality of openings. The second grounding layer may at least partially occlude the first plurality of openings of the first grounding layer when viewed from above the antenna array.

公开(公告)号：US20210359388A1

公开(公告)日：2021-11-18

申请号：US17314219

申请日：2021-05-07

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Mustafa Acar

IPC: H01P5/16 ,  H01L23/66 ,  H01P11/00

Abstract: A power combiner/splitter for multiple input multiple output (MIMO) applications and a method of making the same. A metallisation stack has a plurality of layers including patterned metal features forming first and second branched arrangements of the power combiner/splitter. Each branched arrangement includes a port located at one end of that branched arrangement, and a plurality of further ports. Each branched arrangement also includes a plurality of bifurcated branches extending between each end of that branched arrangement for dividing/combining a signal passing through that branched arrangement between the port and the plurality of further ports. The metallisation stack further includes a common ground plane that is shared by the first and second branched arrangements. At least some of the patterned metal features forming the first branched arrangement overlie at least some of the patterned metal features forming the second branched arrangement.

公开(公告)号：US20190131938A1

公开(公告)日：2019-05-02

申请号：US16119692

申请日：2018-08-31

Applicant: NXP B.V.

Inventor： Jawad Hussain Qureshi ,  Mustafa Acar

IPC: H03F1/56 ,  H03F1/02 ,  H03F3/21 ,  H03F3/19

CPC classification number: H03F1/565 ,  H03F1/0288 ,  H03F1/56 ,  H03F3/19 ,  H03F3/193 ,  H03F3/211 ,  H03F3/24 ,  H03F3/45 ,  H03F2200/09 ,  H03F2200/387 ,  H03F2200/451

Abstract: A power amplifier cell comprising a first power amplifier, a second power amplifier and a balun. The balun comprises a first inductor and a second inductor that define a first transformer; and a third inductor and a fourth inductor that define a second transformer. The following: (i) a parasitic capacitance of the first power amplifier; (ii) a leakage inductance of the first transformer; and (iii) a capacitive coupling between the first inductor and the second inductor, contribute to a first impedance matching circuit for the first power amplifier. Also, the following (iv) a parasitic capacitance of the second power amplifier; (v) a leakage inductance of the second transformer; and (vi) a capacitive coupling between the third inductor and the fourth inductor, contribute to a second impedance matching circuit for the second power amplifier.