公开(公告)号：US20160019140A1

公开(公告)日：2016-01-21

申请号：US14867023

申请日：2015-09-28

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A. Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/02 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US08806068B2

公开(公告)日：2014-08-12

申请号：US13706575

申请日：2012-12-06

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F5/00

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.