公开(公告)号：US20180293205A1

公开(公告)日：2018-10-11

申请号：US15482796

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06F13/40 ,  G11C5/02

CPC classification number: G06F15/8007 ,  G06F9/3004 ,  G06F13/00 ,  G06F13/4027 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/0481 ,  G06N3/063 ,  G06N3/084 ,  G06T1/20

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

公开(公告)号：US12273327B2

公开(公告)日：2025-04-08

申请号：US17935831

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Kylan Race ,  Ernesto Zamora Ramos ,  Jeremy Bottleson ,  Bradley Smith

IPC: H04L9/00 ,  G06V20/40 ,  H04L9/40 ,  H04L67/131

Abstract: An improved AR/VR operation includes receiving, by a server computing device, encrypted AR/VR user data and cleartext metadata associated with the encrypted AR/VR user data from a client computing device; getting server data based at least in part on cleartext metadata; encoding the server data; performing an AR/VR process on the encrypted AR/VR user data and the encoded server data to generate encrypted AR/VR results; and sending the encrypted AR/VR results to the client computing device.

公开(公告)号：US12184622B2

公开(公告)日：2024-12-31

申请号：US17936036

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Ernesto Zamora Ramos ,  Kylan Race ,  Jeremy Bottleson

IPC: H04L29/06 ,  G06T7/70 ,  G06V20/40 ,  G10L25/57 ,  H04L9/00 ,  H04L9/40

Abstract: A method comprises receiving, from a remote device, an audio/video input signal, identifying one or more objects in the audio/video input signal tagged as a sensitive object, evaluating a set of workload requirements for a set of processing workloads comprising portions of the audio/video input signal, selecting one or more heavy processing workloads in the set of processing workloads to send to a compute service provider, in response to a determination that the one or more heavy processing workloads comprises one or more objects tagged as a sensitive object, encrypting the one or more objects tagged as a sensitive object using a homomorphic encryption protocol to generate a first homomorphically encrypted string, and sending the first homomorphically encrypted string to the compute service provider via a privacy protected communication channel.

公开(公告)号：US12112397B2

公开(公告)日：2024-10-08

申请号：US18334733

申请日：2023-06-14

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Altug Koker ,  Narayan Srinivasa ,  Dukhwan Kim ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Feng Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Kevin Nealis ,  Xiaoming Chen ,  Anbang Yao

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

CPC classification number: G06T1/20 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

Abstract: One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

公开(公告)号：US20240171371A1

公开(公告)日：2024-05-23

申请号：US17993561

申请日：2022-11-23

Applicant: Intel Corporation

Inventor： Jeremy Bottleson ,  Kylan Race ,  Ernesto Zamora Ramos ,  Fillipe Dias Moreira De Souza ,  Akshaya Jagannadharao ,  Brad Smith

IPC: H04L9/00 ,  H04L9/06

CPC classification number: H04L9/008 ,  H04L9/0618

Abstract: Homomorphic encryption (HE) acceleration circuitry includes encode circuitry to encode cleartext data into plaintext data, encrypt circuitry to encrypt the plaintext data into HE ciphertext data according to an HE process, decrypt circuitry to decrypt the HE ciphertext data into the plaintext data according to the HE process, and decode circuitry to decode the plaintext data into the cleartext data.

公开(公告)号：US20240086683A1

公开(公告)日：2024-03-14

申请号：US18471843

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Liwei Ma ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Eriko Nurvitadhi ,  Chandrasekaran Sakthivel ,  Barath Lakshmanan ,  Jingyi Jin ,  Justin E. Gottschlich ,  Michael Strickland

IPC: G06N3/044 ,  G06F9/50 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

CPC classification number: G06N3/044 ,  G06F9/5038 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06F2209/5021

Abstract: An apparatus to facilitate workload scheduling is disclosed. The apparatus includes one or more clients, one or more processing units to processes workloads received from the one or more clients, including hardware resources and scheduling logic to schedule direct access of the hardware resources to the one or more clients to process the workloads.

公开(公告)号：US11809978B2

公开(公告)日：2023-11-07

申请号：US17723074

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Liwei Ma ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Eriko Nurvitadhi ,  Chandrasekaran Sakthivel ,  Barath Lakshmanan ,  Jingyi Jin ,  Justin E. Gottschlich ,  Michael Strickland

IPC: G06N3/04 ,  G06N3/044 ,  G06F9/50 ,  G06N3/063 ,  G06N3/084 ,  G06N3/045

CPC classification number: G06N3/044 ,  G06F9/5038 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06F2209/5021

Abstract: An apparatus to facilitate workload scheduling is disclosed. The apparatus includes one or more clients, one or more processing units to processes workloads received from the one or more clients, including hardware resources and scheduling logic to schedule direct access of the hardware resources to the one or more clients to process the workloads.

公开(公告)号：US11727527B2

公开(公告)日：2023-08-15

申请号：US17541413

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Altug Koker ,  Narayan Srinivasa ,  Dukhwan Kim ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Feng Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Kevin Nealis ,  Xiaoming Chen ,  Anbang Yao

IPC: G06T1/20 ,  G06N3/063 ,  G06F9/38 ,  G06F9/30 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06T1/20 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex compute operation.

公开(公告)号：US20230027203A1

公开(公告)日：2023-01-26

申请号：US17826674

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu

IPC: G06F15/80 ,  G06F13/40 ,  G06T1/20 ,  G06F9/30 ,  G06F13/00 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

公开(公告)号：US20220253317A1

公开(公告)日：2022-08-11

申请号：US17683564

申请日：2022-03-01

Applicant: Intel Corporation

Inventor： Liwei Ma ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Eriko Nurvitadhi ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/448

Abstract: A mechanism is described for facilitating fast data operations and for facilitating a finite state machine for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting input data to be used in computational tasks by a computation component of a processor including a graphics processor. The method may further include determining one or more frequently-used data values (FDVs) from the data, and pushing the one or more frequent data values to bypass the computational tasks.