公开(公告)号：US20180300944A1

公开(公告)日：2018-10-18

申请号：US15488641

申请日：2017-04-17

申请人： Intel Corporation

发明人： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC分类号： G06T15/50 ,  G06T15/80 ,  G06T17/20 ,  G06T7/13 ,  G06T7/136 ,  G06T15/00

CPC分类号： G06T15/503 ,  G06T7/13 ,  G06T7/136 ,  G06T15/005

摘要： Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US20180293703A1

公开(公告)日：2018-10-11

申请号：US15483829

申请日：2017-04-10

申请人： Intel Corporation

发明人： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Michael Apodaca ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC分类号： G06T1/60 ,  G06T9/00

摘要： An embodiment of a graphics apparatus may include an embedded local memory, and a memory extender communicatively coupled to the embedded local memory to extend the embedded local memory. The memory extender may be configured to compress information and store the compressed information in the embedded local memory. Additionally, or alternatively, the memory extender may be configured to expose the embedded local memory for non-local access. Other embodiments are disclosed and claimed.

公开(公告)号：US20180286106A1

公开(公告)日：2018-10-04

申请号：US15477028

申请日：2017-04-01

申请人： Intel Corporation

发明人： Michael Apodaca ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Jonathan Kennedy ,  Slawomir Grajewski

IPC分类号： G06T15/20 ,  G06T15/00 ,  G06T7/50 ,  G06T7/70 ,  G06T1/20 ,  G06T3/40

摘要： A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.

公开(公告)号：US20160364828A1

公开(公告)日：2016-12-15

申请号：US14738679

申请日：2015-06-12

申请人： INTEL CORPORATION

发明人： James A. Valerio ,  Abhishek Venkatesh ,  Satyajit Sarangi ,  Michael Apodaca ,  Thomas F. Raoux ,  Hashem Hashemi ,  Rama S.B. Harihara

IPC分类号： G06T1/20

摘要： A mechanism is described for facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance on computing devices. A method of embodiments, as described herein, includes detecting a command stream associated with an application, where the command stream includes dispatches. The method may further include evaluating processing parameters relating to each of the dispatches, where evaluating further includes associating a first plan with one or more of the dispatches to transform the command stream into a transformed command stream. The method may further include associating, based on the first plan, a second plan to the one or more of the dispatches, where the second plan represents the transformed command stream. The method may further include executing the second plan, where execution of the second plan includes processing the transformed command stream in lieu of the command stream.

摘要翻译： 描述了一种机制，用于促进图形处理命令的动态运行时转换，以改善计算设备上的图形性能。 如本文所述的实施例的方法包括检测与应用相关联的命令流，其中命令流包括分派。 该方法还可以包括评估与每个调度有关的处理参数，其中评估进一步包括将第一计划与一个或多个调度相关联，以将命令流变换成变换的命令流。 该方法可以进一步包括：基于第一计划，将第二计划与一个或多个调度相关联，其中第二计划表示变换的命令流。 该方法还可以包括执行第二计划，其中第二计划的执行包括处理变换的命令流来代替命令流。

公开(公告)号：US11636567B2

公开(公告)日：2023-04-25

申请号：US17486330

申请日：2021-09-27

申请人： Intel Corporation

发明人： Abhishek Venkatesh ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC分类号： G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

摘要： An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.

公开(公告)号：US20220262047A1

公开(公告)日：2022-08-18

申请号：US17666193

申请日：2022-02-07

申请人： Intel Corporation

发明人： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer KP ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC分类号： G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

摘要： Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US20220067875A1

公开(公告)日：2022-03-03

申请号：US17467662

申请日：2021-09-07

申请人： Intel Corporation

发明人： Abhishek Venkatesh ,  Selvakumar Panneer

IPC分类号： G06T1/20 ,  G06T17/10 ,  G06T15/80 ,  G06T15/00

摘要： Embodiments described herein are generally directed to conservative rasterization pipeline configurations that allow EarlyZ to be enabled for conservative rasterization. An embodiment of a method includes a conservative rasterizer receiving a primitive to be rasterized. Based on vertices of the primitive, the rasterizer creates a pixel location stream and inner coverage data, indicative of whether the corresponding pixel is fully covered by the primitive or partially covered by the primitive, for each pixel within the pixel location stream. Based on the inner coverage data, pixels of the pixel location stream are grouped into a first group including those of the pixels that are fully covered by the primitive and a second group including those of pixels that are partially covered by the primitive. Separate pixel shader threads are then launched by the rasterizer for blocks of pixels of the first group and blocks of pixels of the second group.

公开(公告)号：US11263720B2

公开(公告)日：2022-03-01

申请号：US16985329

申请日：2020-08-05

申请人： Intel Corporation

发明人： Saurabh Sharma ,  Abhishek Venkatesh ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  Altug Koker ,  Aravindh V. Anantaraman ,  Pattabhiraman P. K. ,  Abhishek R. Appu ,  Joydeep Ray ,  Kamal Sinha ,  Vasanth Ranganathan ,  Bhushan M. Borole ,  Wenyin Fu ,  Eric J. Hoekstra ,  Linda L. Hurd

IPC分类号： G06T1/20 ,  G06T1/60 ,  G06T15/00

摘要： A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

公开(公告)号：US11062506B2

公开(公告)日：2021-07-13

申请号：US16916875

申请日：2020-06-30

申请人： Intel Corporation

发明人： Andrew T. Lauritzen ,  Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  David M. Cimini ,  Karthik Vaidyanathan ,  Abhishek Venkatesh ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC分类号： G06T15/40 ,  G06T15/80 ,  G06T15/00 ,  G06T17/20 ,  G06T15/06 ,  G06T1/20 ,  G06T15/30

摘要： An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

公开(公告)号：US20210035257A1

公开(公告)日：2021-02-04

申请号：US16985329

申请日：2020-08-05

申请人： Intel Corporation

发明人： Saurabh Sharma ,  Abhishek Venkatesh ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  Altug Koker ,  Aravindh V. Anantaraman ,  Pattabhiraman P. K. ,  Abhishek R. Appu ,  Joydeep Ray ,  Kamal Sinha ,  Vasanth Ranganathan ,  Bhushan M. Borole ,  Wenyin Fu ,  Eric J. Hoekstra ,  Linda L. Hurd

IPC分类号： G06T1/20 ,  G06T1/60 ,  G06T15/00

摘要： A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.