- 专利标题: CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER
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申请号: US17666193申请日: 2022-02-07
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公开(公告)号: US20220262047A1公开(公告)日: 2022-08-18
- 发明人: Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer KP , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: G06T11/00
- IPC分类号: G06T11/00 ; G06T1/20 ; G06T1/60 ; G06T15/00
摘要:
Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
公开/授权文献
- US11869119B2 Controlling coarse pixel size from a stencil buffer 公开/授权日:2024-01-09
信息查询
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T11/00 | 2D〔二维〕图像的生成 |