公开(公告)号：US07378872B1

公开(公告)日：2008-05-27

申请号：US11445620

申请日：2006-06-02

申请人： Om P. Agrawal ,  Barry Britton ,  Xiaojie He ,  Sajitha Wijesuriya ,  Ming H. Ding ,  Jun Zhao

发明人： Om P. Agrawal ,  Barry Britton ,  Xiaojie He ,  Sajitha Wijesuriya ,  Ming H. Ding ,  Jun Zhao

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17728

摘要： Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks, with at least one of the programmable logic blocks having at least a first, a second, and a third logic block slice of different logic block slice types.

摘要翻译： 本文公开了系统和方法，以根据本发明的实施例提供逻辑块片段架构和可编程逻辑块架构以及控制逻辑架构。 例如，根据本发明的实施例，可编程逻辑器件包括多个可编程逻辑块，其中至少一个可编程逻辑块具有至少第一，第二和第三逻辑块片 不同的逻辑块片类型。

公开(公告)号：US07327159B1

公开(公告)日：2008-02-05

申请号：US11287720

申请日：2005-11-28

申请人： Om P. Agrawal ,  Ravindar M. Lall ,  David L. Rutledge ,  Tom Gustafson

发明人： Om P. Agrawal ,  Ravindar M. Lall ,  David L. Rutledge ,  Tom Gustafson

IPC分类号： H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17796

摘要： In accordance with an embodiment of the present invention, a programmable logic device includes a memory adapted to store information in the programmable logic device, an input/output circuit adapted to transfer information into or out of the programmable logic device, and an interconnect architecture adapted to route information within the programmable logic device. An interface circuit is provided to couple the memory and the input/output circuit to the interconnect architecture.

摘要翻译： 根据本发明的实施例，可编程逻辑器件包括适于在可编程逻辑器件中存储信息的存储器，适于将信息传入或传出可编程逻辑器件的输入/输出电路，以及适配器 以在可编程逻辑器件内路由信息。 提供接口电路以将存储器和输入/输出电路耦合到互连体系结构。

公开(公告)号：US07154298B1

公开(公告)日：2006-12-26

申请号：US10022464

申请日：2001-12-14

申请人： Om P. Agrawal ,  Jinghui Zhu

发明人： Om P. Agrawal ,  Jinghui Zhu

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17744

摘要： A programmable interconnect circuit comprising a plurality of I/O cells arranged into blocks includes a routing structure for each block, wherein each routing structure may programmably route signals between its block's I/O cells and the I/O cells within the remaining blocks.

摘要翻译： 包括布置成块的多个I / O单元的可编程互连电路包括用于每个块的路由结构，其中每个路由结构可编程地在其块的I / O单元与剩余块内的I / O单元之间路由信号。

公开(公告)号：US07028281B1

公开(公告)日：2006-04-11

申请号：US10194771

申请日：2002-07-12

申请人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler

发明人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler

IPC分类号： G06F17/50

CPC分类号： H03K19/17736 ,  G06F17/5054 ,  H01L2924/0002 ,  H03K19/17728 ,  H03K19/17784 ,  H01L2924/00

摘要： Field programmable gate arrays (FPGA's) may be structured in accordance with the disclosure to have a register-intensive architecture that provides, for each of plural function-spawning LookUp Tables (e.g. a 4-input, base LUT's) within a logic block, a plurality of in-block accessible registers. A register-feeding multiplexer means may be provided for allowing each of the plural registers to equivalently capture and store a result signal output by the corresponding, base LUT of the plural registers. Registerable, primary and secondary feedthroughs may be provided for each base LUT so that locally-acquired input signals of the LUT may be fed-through to the corresponding, in-block registers for register-recovery purposes without fully consuming (wasting) the lookup resources of the associated, base LUT. A multi-stage, input switch matrix (ISM) may be further provided for acquiring and routing input signals from adjacent, block-interconnect lines (AIL's) and/or block-intra-connect lines (e.g., FB's) to the base LUT's and/or their respective, registerable feedthroughs. Techniques are disclosed for utilizing the many in-block registers and/or the registerable feedthroughs and/or the multi-stage ISM's for efficiently implementing various circuit designs by appropriately configuring such register-intensive FPGA's.

摘要翻译： 现场可编程门阵列（FPGA）可以根据本公开进行结构化以具有寄存器密集型架构，其针对逻辑块内的多个功能产生查找表（例如，4输入，基本LUT）中的每一个提供寄存器密集型结构， 多个块内可访问寄存器。 可以提供寄存器馈送多路复用器装置，用于允许多个寄存器中的每一个等效地捕获并存储由多个寄存器的相应的基本LUT输出的结果信号。 可以为每个基本LUT提供可登记的主和辅助馈通，使得LUT的本地采集的输入信号可以被馈送到相应的块内寄存器用于寄存器恢复目的，而不会完全消耗（浪费）查找资源 的相关的基本LUT。 可以进一步提供多级输入开关矩阵（ISM），用于从相邻的块互连线（AIL）和/或块内连接线（例如，FB）到基本LUT的采集和路由输入信号，并且 /或其各自的可注册馈通。 公开了利用许多块内寄存器和/或可注册馈通和/或多级ISM的技术来通过适当地配置这种寄存器密集型FPGA来有效地实现各种电路设计。

公开(公告)号：US06861868B1

公开(公告)日：2005-03-01

申请号：US10463781

申请日：2003-06-16

申请人： Om P. Agrawal ,  Jinghui Zhu ,  Kuang Chi ,  ChienKuang Chen

发明人： Om P. Agrawal ,  Jinghui Zhu ,  Kuang Chi ,  ChienKuang Chen

IPC分类号： H01L21/82 ,  H03K19/177 ,  H03K19/173

CPC分类号： H03K19/17744

摘要： A programmable semiconductor device comprising a plurality of I/O circuits arranged into blocks includes a routing structure for each block, wherein each routing structure may programmably route signals between its block's I/O circuits and the I/O circuits within the remaining blocks. Each I/O circuit associates with a pin such that each block has a set of pins. A SERDES and a FIFO buffer associate with each block. Each block's SERDES couples between the block's I/O circuits and the block's set of pins. Each FIFO buffer couples between the SERDES and its block's I/O circuits.

摘要翻译： 包括布置成块的多个I / O电路的可编程半导体器件包括用于每个块的路由结构，其中每个路由结构可以在其块的I / O电路与剩余块内的I / O电路之间编程地路由信号。 每个I / O电路与引脚相关联，使得每个块具有一组引脚。 SERDES和FIFO缓冲区与每个块相关联。 每个块的SERDES耦合在块的I / O电路和块的引脚组之间。 每个FIFO缓冲器耦合在SERDES和其块的I / O电路之间。

公开(公告)号：US06184713B2

公开(公告)日：2001-02-06

申请号：US09326940

申请日：1999-06-06

申请人： Om P. Agrawal ,  Claudia A. Stanley ,  Xiaojie (Warren) He ,  Larry R. Metzger ,  Robert A. Simon ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  Claudia A. Stanley ,  Xiaojie (Warren) He ,  Larry R. Metzger ,  Robert A. Simon ,  Kerry A. Ilgenstein

IPC分类号： H01L2500

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/1778

摘要： An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications. The large number of parallel inputs to each SLB ease implementation of 64-bit wide designs. Symmetry within the design of each segment allow for more finely-granulated implementations such as for 32 or 16-bit wide designs.

摘要翻译： 改进的，可扩展的CPLD设备具有由全局交换矩阵（GSM）和偶数段分段交换矩阵（SSM）组成的双层分层交换结构。 偶数个超级逻辑块（SLB）耦合到每个SSM。 每个SSM及其SLB定义了一个与GSM相连的段。 每个SLB具有相对较多的输入（至少80），并且可以生成作为从SSM向SLB输入提供的独立输入项的乘积的产品项信号（PT）。 每个SLB中生成的某些产品术语专用于SLB本地控件。 每个SLB具有至少32个宏单元和至少16个I / O焊盘，其向本地SSM和全球GSM反馈。 在每个段内确保100％的段内连接性，以便每个段可用作独立的小型CPLD。 每个SSM都有额外的线路，专用于分段（全球）通信。 每个SLB的大量并行输入轻松实现64位宽的设计。 每个片段设计中的对称性允许更精细的粒化实现，例如32或16位宽的设计。

公开(公告)号：US06181163B2

公开(公告)日：2001-01-30

申请号：US09235351

申请日：1999-01-21

申请人： Om P. Agrawal ,  Herman M. Chang ,  Bradley A. Sharpe-Geisler ,  Bai Nguyen

发明人： Om P. Agrawal ,  Herman M. Chang ,  Bradley A. Sharpe-Geisler ,  Bai Nguyen

IPC分类号： H03K19177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.

摘要翻译： 具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多个嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。 每个嵌入式存储块具有用于捕获接收的地址信号的地址端口和用于捕获所提供的控制信号的控制端口。 提供互连资源，包括用于以广播或窄播为基础将共享地址和控制信号传送到多个存储器块的存储器控​​制传送互连信道（MCIC）。

公开(公告)号：US6124730A

公开(公告)日：2000-09-26

申请号：US212022

申请日：1998-12-15

申请人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Herman M. Chang ,  Bai Nguyen ,  Giap H. Tran

发明人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Herman M. Chang ,  Bai Nguyen ,  Giap H. Tran

IPC分类号： H03K19/173 ,  H03K19/177 ,  H01L25/00

CPC分类号： H03K19/17748 ,  H03K19/1737 ,  H03K19/17736 ,  H03K19/17756 ,  H03K19/1778

摘要： A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB's may be synthetically combined to efficiently define higher order, N:1 DyMUX's.

摘要翻译： 可变格式架构（VGA）用于从原始构建元素（CBE）合成每个给定任务的适当量的动态复用能力。 这些可配置构建单元（CBE）中的未使用的组合被重新配置以执行进一步的逻辑功能来代替动态复用功能。 每个CBE可以可编程地配置为提供不超过2对1的动态多路复用器（2：1 DyMUX）。 然后可以将这种合成的2:1 DyMUX的动态可选输出输出到共享互连线上。 CBE的对可以合成，以有效地定义4：1的DyMUX，每个这样的4：1多路复用器占用可配置的构建块（CBB）结构。 CBB的对可以合成组合，以有效地定义8：1 DyMUX，每个这样合成的8：1多路复用器占据L形VGB结构（可变颗粒块）的垂直或水平延伸的腿部分。 然后，VGB的如此配置的腿部分可以将由其8：1 DyMUX选择的信号输出到由VGB支路驱动的共享互连线上。 VGB的对或四重组可以合成组合，以有效地定义高阶N：1 DyMUX。

公开(公告)号：US6097664A

公开(公告)日：2000-08-01

申请号：US235356

申请日：1999-01-21

申请人： Bai Nguyen ,  Bradley A. Sharpe-Geisler ,  Herman M. Chang ,  Om P. Agrawal

发明人： Bai Nguyen ,  Bradley A. Sharpe-Geisler ,  Herman M. Chang ,  Om P. Agrawal

IPC分类号： G11C8/16 ,  G11C8/00

CPC分类号： G11C8/16

摘要： A serial scan chain extends into an array of SRAM cells within a multi-ported memory system for allowing serial introduction of write data into the SRAM cells and serial read-back of the data. Initial data may be pre-loaded into the SRAM cells by way of the serial scan chain before being read parallel-wise in response to read requests submitted through any of multiple, parallel data access ports of the system.

摘要翻译： 串行扫描链扩展到多端口存储器系统中的SRAM单元阵列，用于将写入数据串行引入SRAM单元和数据的串行读回。 响应于通过系统的多个并行数据访问端口中的任何一个提交的读取请求，初始数据可以通过串行扫描链预先加载到SRAM单元中，然后以并行方式读取。

公开(公告)号：US6097212A

公开(公告)日：2000-08-01

申请号：US948306

申请日：1997-10-09

申请人： Om P. Agrawal ,  Herman M. Chang ,  Bradley A. Sharpe-Geisler ,  Giap H. Tran

发明人： Om P. Agrawal ,  Herman M. Chang ,  Bradley A. Sharpe-Geisler ,  Giap H. Tran

IPC分类号： H03K19/173 ,  H03K19/177 ,  H01L25/00

CPC分类号： H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17792 ,  H03K19/17796 ,  H01L2924/0002

摘要： A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2xL, 4xL, 8xL and direct connect surround each super-VGB to provide different kinds of interconnect.