公开(公告)号：US10833722B1

公开(公告)日：2020-11-10

申请号：US16657998

申请日：2019-10-18

申请人： Grant Thomas Jennings ,  Jinghui Zhu ,  Jianhua Liu

发明人： Grant Thomas Jennings ,  Jinghui Zhu ,  Jianhua Liu

IPC分类号： H04B1/40 ,  H03K19/17772 ,  H03K19/17736 ,  H03K19/17724

摘要： A semiconductor device contains an integrated circuit (“IC”) capable of being selectively programmed to perform one or more logic functions. The device, in one embodiment, includes multiple logic blocks (“LBs”), a routing fabric, and a configurable wireless communication block (“WCB”). The configurable LBs is able to be selectively programmed to perform one or more logic functions. The routing fabric is used to route information between the configurable LBs and input/output ports based on a routing configuration signals. The configurable WCB, having a control circuit and a built-in transceiver, is configured to facilitate transmitting information between the IC and an external system via a wireless communications network.

公开(公告)号：US10990160B2

公开(公告)日：2021-04-27

申请号：US16361112

申请日：2019-03-21

申请人： Jinghui Zhu

发明人： Jinghui Zhu

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F1/3296 ,  G06F30/34 ,  G06F1/3246 ,  G06F1/3234

摘要： A programmable semiconductor integrated circuit fabricated on a single microchip device capable of being selectively programmed to perform one or more logic functions provides a sleep mode using an intermittent power saving logic. The circuit includes configurable logic blocks (“LB”), memory, switch, and sleep controller. While LB can enter a power saving sleep mode (“PSSM”) in accordance with its power supply, the memory stores the configuration information for the LB. The switch is configured to manage the LB power supply based on a configurable sleep signal for facilitating the PSSM. The sleep controller facilitates generation of the configurable sleep signal in response to the signal from a power saving output port associated with the LB.

公开(公告)号：US06661254B1

公开(公告)日：2003-12-09

申请号：US10021873

申请日：2001-12-14

申请人： Om P. Agrawal ,  Jinghui Zhu ,  Kuang Chi ,  ChienKuang Chen

发明人： Om P. Agrawal ,  Jinghui Zhu ,  Kuang Chi ,  ChienKuang Chen

IPC分类号： H01L2500

CPC分类号： H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03L7/07 ,  H03L7/081 ,  H03L7/18

摘要： A programmable interconnect circuit includes a phase-locked loop configured to provide an internal clock signal to I/O cells in the programmable interconnect circuit such that registers in the I/O cells may all be clocked in phase. In addition, the phase-locked loop may provide an external clock signal to the programmable interconnect circuit's routing structure such that external devices may clocked in phase with the external clock signal.

摘要翻译： 可编程互连电路包括被配置为向可编程互连电路中的I / O单元提供内部时钟信号的锁相环，使得I / O单元中的寄存器都可以同相计时。 此外，锁相环可以向可编程互连电路的路由结构提供外部时钟信号，使得外部设备可以与外部时钟信号同相计时。

公开(公告)号：US20200301498A1

公开(公告)日：2020-09-24

申请号：US16361112

申请日：2019-03-21

申请人： Jinghui Zhu

发明人： Jinghui Zhu

IPC分类号： G06F1/3296 ,  G06F1/3234 ,  G06F1/3246 ,  G06F17/50

摘要： A programmable semiconductor integrated circuit fabricated on a single microchip device capable of being selectively programmed to perform one or more logic functions provides a sleep mode using an intermittent power saving logic. The circuit includes configurable logic blocks (“LB”), memory, switch, and sleep controller. While LB can enter a power saving sleep mode (“PSSM”) in accordance with its power supply, the memory stores the configuration information for the LB. The switch is configured to manage the LB power supply based on a configurable sleep signal for facilitating the PSSM. The sleep controller facilitates generation of the configurable sleep signal in response to the signal from a power saving output port associated with the LB.

公开(公告)号：US07208975B1

公开(公告)日：2007-04-24

申请号：US11040772

申请日：2005-01-20

申请人： Om P. Agrawal ,  Jock Tomlinson ,  Kuang Chi ,  Ji Zhao ,  Ju Shen ,  Jinghui Zhu

发明人： Om P. Agrawal ,  Jock Tomlinson ,  Kuang Chi ,  Ji Zhao ,  Ju Shen ,  Jinghui Zhu

IPC分类号： H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17744

摘要： In one embodiment, a programmable interconnect includes SERDES circuits dedicated to communicating high-speed data and input/output (I/O) circuits dedicated to communicating low-speed data. A routing structure is configurable to couple a SERDES circuit to another SERDES circuit, a SERDES circuit to an I/O circuit, an I/O circuit to a SERDES circuit, and an I/O circuit to another I/O circuit over routing paths having deterministic routing delays. In another embodiment, the routing structure includes a high-speed routing structure for communicating high-speed data to and from a SERDES circuit and a low-speed routing structure for communicating low-speed data to and from an I/O circuit.

摘要翻译： 在一个实施例中，可编程互连包括专用于传送高速数据的SERDES电路和专用于传送低速数据的输入/输出（I / O）电路。 布线结构可配置为将SERDES电路耦合到另一个SERDES电路，到I / O电路的SERDES电路，到SERDES电路的I / O电路以及通过路由路径到另一个I / O电路的I / O电路 具有确定性的路由延迟。 在另一个实施例中，路由结构包括用于向SERDES电路传送高速数据和从SERDES电路传送高速数据的高速路由结构以及用于向I / O电路传送低速数据的低速路由结构。

公开(公告)号：US06777979B1

公开(公告)日：2004-08-17

申请号：US10334642

申请日：2002-12-31

申请人： Jinghui Zhu ,  Jin Ni ,  Ju Shen ,  Tong-Sheng Wang

发明人： Jinghui Zhu ,  Jin Ni ,  Ju Shen ,  Tong-Sheng Wang

IPC分类号： H03K19177

CPC分类号： H03K19/17744

摘要： A FIFO coordinates with registers of a programmable semiconductor device, wherein the registers are clocked according to an internal clock and words are written into the FIFO according to a write clock. The FIFO includes a read counter responsive to the internal clock to identify a current read address in the FIFO. At a given cycle of the internal clock, the word stored at the current read address of the FIFO may be registered within the registers of the programmable semiconductor device.

摘要翻译： FIFO与可编程半导体器件的寄存器协调，其中寄存器根据内部时钟计时，并且根据写时钟将字写入FIFO。 FIFO包括响应于内部时钟的读取计数器，以识别FIFO中的当前读取地址。 在内部时钟的给定周期，存储在FIFO的当前读取地址处的字可以被注册在可编程半导体器件的寄存器内。

公开(公告)号：US06703860B1

公开(公告)日：2004-03-09

申请号：US10021844

申请日：2001-12-14

申请人： Om P. Agrawal ,  Jinghui Zhu

发明人： Om P. Agrawal ,  Jinghui Zhu

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17744

摘要： A programmable interconnect circuit comprising a plurality of I/O cells arranged into I/O blocks includes a routing structure for each I/O block, wherein each routing structure may programmably route signals between the plurality of I/O cells and the I/O cells within its I/O block. Each I/O cell includes a multiplexer and an I/O circuit associated with a pin of the programmable interconnect circuit. Associated with each I/O block is a control array receiving control signals from its routing structure. An AND array in the control array produces a set of product term control signals for its I/O block from the received control signals.

摘要翻译： 包括布置在I / O块中的多个I / O单元的可编程互连电路包括用于每个I / O块的路由结构，其中每个路由结构可编程地在多个I / O单元与I / O单元之间路由信号 其I / O块内的单元。 每个I / O单元包括多路复用器和与可编程互连电路的引脚相关联的I / O电路。 与每个I / O块相关联的是从其路由结构接收控制信号的控制阵列。 控制阵列中的AND阵列从接收的控制信号产生一组其I / O块的产品项控制信号。

公开(公告)号：US10789197B2

公开(公告)日：2020-09-29

申请号：US15977925

申请日：2018-05-11

申请人： Jinghui Zhu

发明人： Jinghui Zhu

IPC分类号： G06F13/00 ,  G06F13/42 ,  G06F13/40 ,  G06F13/38

摘要： One embodiment of the present invention discloses a configurable microcontroller unit (“CMU”) capable of providing one or more programmable input and output (“I/O”) interfaces. The CMU includes a processor, I/O ports, and programmable microcontroller (“PM”). The processor is configured to communicate with a host central processing unit (“CPU”) based on a set of predefined instruction code. The I/O ports are used to transmit information between the processor and an external device. The PM facilitates communication interfaces between the I/O ports and one or more external devices via one or more configurable communication standards selected by the PM in accordance with interface programming microcode.

公开(公告)号：US20200145009A1

公开(公告)日：2020-05-07

申请号：US16730716

申请日：2019-12-30

申请人： Jinghui Zhu ,  Jianhua Liu ,  Ning Song

发明人： Jinghui Zhu ,  Jianhua Liu ,  Ning Song

IPC分类号： H03K19/17784 ,  H03K19/17724

摘要： A programmable semiconductor device capable of being selectively programmed to perform one or more logic functions includes a first region, second region, first regional power control (“RPC”), and second-to-first power control connection. The first region, in one embodiment, contains first configurable logic blocks (“CLBs”) able to be selectively programmed to perform a first logic function. The second region includes a group of second CLBs configured to be selectively programmed to perform a second logic function. The first RPC port or inter-chip port which is coupled between the first and second regions facilitates dynamic power supply to the first region in response to the data in the second region. The second-to-first power control connection is used to allow the second region to facilitate and/or control power to the first region.

公开(公告)号：US07245154B1

公开(公告)日：2007-07-17

申请号：US11071356

申请日：2005-03-03

申请人： Allan T. Davidson ,  Jinghui Zhu

发明人： Allan T. Davidson ,  Jinghui Zhu

IPC分类号： H03K19/0175

CPC分类号： H03K19/00346

摘要： In one embodiment, a circuit is provided that includes: a differential input receiver having a first input terminal and a second input terminal; a first programmable switch coupled to the first input terminal and coupled through a first resistor to a first voltage such that if the first programmable switch is closed, the first input terminal is pulled towards the first voltage; and a second programmable switch coupled to the second input terminal and coupled through a second resistor to a second voltage such that if the second programmable switch is closed, the second input terminal is pulled towards the second voltage, wherein the first and second programmable switches are programmed to be closed during a differential input mode of operation in which the differential input receiver processes differential input signals provided to the first and second input terminals.

摘要翻译： 在一个实施例中，提供一种电路，其包括：具有第一输入端和第二输入端的差分输入接收器; 第一可编程开关，其耦合到所述第一输入端并通过第一电阻器耦合到第一电压，使得如果所述第一可编程开关闭合，则将所述第一输入端子拉向所述第一电压; 以及第二可编程开关，其耦合到所述第二输入端子并且通过第二电阻器耦合到第二电压，使得如果所述第二可编程开关闭合，则所述第二输入端子被拉向所述第二电压，其中所述第一和第二可编程开关是 被编程为在差分输入接收器处理提供给第一和第二输入端子的差分输入信号的差分输入操作模式期间闭合。