公开(公告)号：US07605606B1

公开(公告)日：2009-10-20

申请号：US11498646

申请日：2006-08-03

Applicant: Ming H. Ding ,  Sajitha Wijesuriya ,  Jun Zhao ,  Om P. Agrawal ,  Barry Britton ,  Xiaojie He

Inventor： Ming H. Ding ,  Sajitha Wijesuriya ,  Jun Zhao ,  Om P. Agrawal ,  Barry Britton ,  Xiaojie He

IPC: H03K19/177

CPC classification number: H03K19/17736

Abstract: Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks. A first routing circuit provides global signal routing within the programmable logic device for the corresponding programmable logic block. A first input routing circuit receives signals from the first routing circuit and routes the signals to the logic block slices within the corresponding programmable logic block.

Abstract translation: 系统和方法为可编程逻辑块提供可编程逻辑块架构和路由架构。 例如，根据本发明的实施例，可编程逻辑器件包括多个可编程逻辑块和每个可编程逻辑块内的多个逻辑块片。 第一路由电路在可编程逻辑器件内为相应的可编程逻辑块提供全局信号路由。 第一输入路由电路从第一路由电路接收信号并将信号路由到相应的可编程逻辑块内的逻辑块片段。

公开(公告)号：US07532646B2

公开(公告)日：2009-05-12

申请号：US11064477

申请日：2005-02-23

Applicant: Wai-Bor Leung ,  Barry Britton ,  Akila Subramaniam

Inventor： Wai-Bor Leung ,  Barry Britton ,  Akila Subramaniam

IPC: H04J3/06 ,  H04J3/02

CPC classification number: H04L25/14

Abstract: A channel-alignment circuit has a controller and a plurality of channel-alignment blocks. Each channel-alignment block synchronizes two or more channels. The controller coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.

Abstract translation: 通道对准电路具有控制器和多个通道对准块。 每个通道对齐块同步两个或更多个通道。 控制器通过块协调通道的同步，使得（i）两个或更多个块的一个或多个组中的每一个中的信道被同步，并且（ii）每组块独立于任何其他组同步。

公开(公告)号：US08319521B1

公开(公告)日：2012-11-27

申请号：US13076300

申请日：2011-03-30

Applicant: Wei Han ,  Barry Britton ,  Eric Lee ,  Zheng Chen ,  Warren Juenemann ,  Mose Wahlstrom

Inventor： Wei Han ,  Barry Britton ,  Eric Lee ,  Zheng Chen ,  Warren Juenemann ,  Mose Wahlstrom

IPC: H03K19/177 ,  H01L25/00

CPC classification number: H03K19/17764 ,  H03K19/17768

Abstract: A programmable logic device (PLD) is disclosed that includes a non-volatile memory; a shadow register; and a data shift register (DSR) configurable to receive control information from an external programming tool, wherein the DSR is configured to shift the control information into the shadow register if the PLD is in a first programming mode, the PLD being configurable to operate in the first programming mode using the control information stored in the shadow register without the control information being stored in the non-volatile memory.

Abstract translation: 公开了一种包括非易失性存储器的可编程逻辑器件（PLD）; 影子寄存器 以及数据移位寄存器（DSR），其被配置为从外部编程工具接收控制信息，其中所述DSR被配置为如果所述PLD处于第一编程模式，则将所述控制信息移位到所述影子寄存器中，所述PLD可配置为在 使用存储在影子寄存器中的控制信息的第一编程模式，而不将控制信息存储在非易失性存储器中。

公开(公告)号：US07599457B2

公开(公告)日：2009-10-06

申请号：US11199287

申请日：2005-08-08

Applicant: Phillip Johnson ,  Zheng Chen ,  Barry Britton

Inventor： Phillip Johnson ,  Zheng Chen ,  Barry Britton

IPC: H04L7/02

CPC classification number: H04L7/0338 ,  H03L7/0812

Abstract: In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.

Abstract translation: 在本发明的一个实施例中，时钟和数据恢复（CDR）系统具有产生多个相位偏移时钟信号的多相时钟发生器和一个或多个信道电路，每个信道电路接收（不同的）输入 数据信号和所有相位偏移时钟信号，并产生输出数据流和恢复的时钟信号。 每个通道电路具有多个数据寄存器（例如，触发器），每个数据寄存器在其时钟输入端口接收输入数据信号，并在其数据输入端口接收不同的相位偏移时钟信号， 触发器在输入数据信号的每个（上升沿）触发。 通道电路处理来自不同触发器的输出以选择合适的相位偏移时钟信号，以用于对输入数据信号进行采样以产生输出数据流，其中从所选择的相位偏移时钟产生恢复的时钟信号 信号。

公开(公告)号：US20060187966A1

公开(公告)日：2006-08-24

申请号：US11064477

申请日：2005-02-23

Applicant: Wai-Bor Leung ,  Barry Britton ,  Akila Subramaniam

Inventor： Wai-Bor Leung ,  Barry Britton ,  Akila Subramaniam

IPC: H04J3/06

CPC classification number: H04L25/14

Abstract: A channel-alignment circuit has a controller and a plurality of channel-alignment blocks. Each channel-alignment block synchronizes two or more channels. The controller coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.

公开(公告)号：US08314634B1

公开(公告)日：2012-11-20

申请号：US13079578

申请日：2011-04-04

Applicant: Barry Britton ,  Richard Booth ,  Yang Xu ,  Tawei David Li

Inventor： Barry Britton ,  Richard Booth ,  Yang Xu ,  Tawei David Li

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K19/018521 ,  H03K19/00361

Abstract: Techniques are provided to reduce glitches at an output signal node when a device is switched to and from a low power operation mode. In one example, a method of operating a device includes providing power to operate a signal source of the device during a normal operation mode of the device. The method also includes passing an output signal from the signal source through a signal path to an output node during the normal operation mode. The method also includes receiving an operation mode signal to switch the device from the normal operation mode to a low power operation mode. The method also includes disabling the signal path to prevent glitches from appearing at the output node during the switch from the normal operation mode to the low power operation mode. The method also includes continuing providing power to the signal source until after the signal path is disabled.

Abstract translation: 当设备切换到低功率操作模式时，提供技术来减少输出信号节点处的毛刺。 在一个示例中，操作设备的方法包括在设备的正常操作模式期间提供用于操作设备的信号源的电力。 该方法还包括在正常操作模式期间将来自信号源的输出信号通过信号路径传送到输出节点。 该方法还包括接收操作模式信号以将设备从正常操作模式切换到低功率操作模式。 该方法还包括禁用信号路径以防止在从正常操作模式切换到低功率操作模式期间在输出节点处出现毛刺。 该方法还包括在信号路径被禁用之后继续向信号源供电。

公开(公告)号：US07696784B1

公开(公告)日：2010-04-13

申请号：US12105959

申请日：2008-04-18

Applicant: Om P. Agrawal ,  Xiaojie He ,  Sajitha Wijesuriya ,  Barry Britton ,  Ming H. Ding ,  Jun Zhao

Inventor： Om P. Agrawal ,  Xiaojie He ,  Sajitha Wijesuriya ,  Barry Britton ,  Ming H. Ding ,  Jun Zhao

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17728

Abstract: In one embodiment, a programmable logic device includes a plurality of programmable logic blocks and a plurality of slices within each of the programmable logic blocks. At least one programmable logic blocks includes a first slice not adapted to provide register functionality or RAM functionality, a second slice adapted to provide register functionality but not RAM functionality, and a third slice adapted to provide register functionality and RAM functionality. Control logic within the programmable logic block is adapted to provide control signals at the programmable block level and at the slice level.

Abstract translation: 在一个实施例中，可编程逻辑器件包括多个可编程逻辑块和每个可编程逻辑块内的多个片。 至少一个可编程逻辑块包括不适于提供寄存器功能或RAM功能的第一片，适于提供寄存器功能而不是RAM功能的第二片，以及适于提供寄存器功能和RAM功能的第三片。 可编程逻辑块内的控制逻辑适于在可编程块级和限幅级提供控制信号。

公开(公告)号：US07592834B1

公开(公告)日：2009-09-22

申请号：US12164265

申请日：2008-06-30

Applicant: Om P. Agrawal ,  Xiaojie He ,  Sajitha Wijesuriya ,  Barry Britton ,  Ming H. Ding ,  Jun Zhao

Inventor： Om P. Agrawal ,  Xiaojie He ,  Sajitha Wijesuriya ,  Barry Britton ,  Ming H. Ding ,  Jun Zhao

IPC: H03K19/173

CPC classification number: H03K19/17736 ,  H03K19/17728

Abstract: In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one programmable logic block includes a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register. The programmable logic block further includes control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data stored within the configuration memory.

Abstract translation: 在本发明的一个实施例中，可编程逻辑器件包括适于存储配置数据和多个可编程逻辑块的配置存储器。 至少一个可编程逻辑块包括多个双切片逻辑块，每个双切片逻辑块包括第一和第二切片，每个切片包括至少两个查找表（LUT）和寄存器。 可编程逻辑块还包括适于在可编程块级别，双切片块级别和寄存器级别分别选择控制信号的控制逻辑，该控制逻辑响应于存储在配置存储器内的配置数据。

公开(公告)号：US20070030936A1

公开(公告)日：2007-02-08

申请号：US11199287

申请日：2005-08-08

Applicant: Phillip Johnson ,  Zheng Chen ,  Barry Britton

Inventor： Phillip Johnson ,  Zheng Chen ,  Barry Britton

IPC: H04L7/00

CPC classification number: H04L7/0338 ,  H03L7/0812

Abstract: In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.

Abstract translation: 在本发明的一个实施例中，时钟和数据恢复（CDR）系统具有产生多个相位偏移时钟信号的多相时钟发生器和一个或多个信道电路，每个信道电路接收（不同的）输入 数据信号和所有相位偏移时钟信号，并产生输出数据流和恢复的时钟信号。 每个通道电路具有多个数据寄存器（例如，触发器），每个数据寄存器在其时钟输入端口接收输入数据信号，并在其数据输入端口接收不同的相位偏移时钟信号， 触发器在输入数据信号的每个（上升沿）触发。 通道电路处理来自不同触发器的输出以选择合适的相位偏移时钟信号，以用于对输入数据信号进行采样以产生输出数据流，其中从所选择的相位偏移时钟产生恢复的时钟信号 信号。

公开(公告)号：US06940779B2

公开(公告)日：2005-09-06

申请号：US10641260

申请日：2003-08-13

Applicant: Zheng (Jeff) Chen ,  John Schadt ,  Barry Britton

Inventor： Zheng (Jeff) Chen ,  John Schadt ,  Barry Britton

IPC: H03K19/177 ,  G11C7/00

CPC classification number: H03K19/17772 ,  H03K19/17756 ,  H03K19/1776 ,  H03K19/17764

Abstract: Systems and methods are disclosed herein to initialize memory blocks of a programmable logic device. For example in accordance with an embodiment of the present invention, a system bus extension is provided for the memory blocks that functions as a unidirectional broadcasting write bus. A read bus may also be provided to read data stored in the memory blocks.