公开(公告)号：US20100244045A1

公开(公告)日：2010-09-30

申请号：US12795143

申请日：2010-06-07

Applicant: Manabu YANAGIHARA ,  Kazushi Nakazawa ,  Tsuyoshi Tanaka

Inventor： Manabu YANAGIHARA ,  Kazushi Nakazawa ,  Tsuyoshi Tanaka

IPC: H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/7787 ,  H01L29/872

Abstract: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.

Abstract translation: 半导体器件包括形成在衬底上的第一半导体层，形成在第一半导体层上彼此间隔开的肖特基电极和欧姆电极以及形成为覆盖第一半导体层的第二半导体层 肖特基电极和欧姆电极暴露。 第二半导体层具有比第一半导体层更大的带隙。

公开(公告)号：US07800097B2

公开(公告)日：2010-09-21

申请号：US11299818

申请日：2005-12-13

Applicant: Yutaka Hirose ,  Tsuyoshi Tanaka

Inventor： Yutaka Hirose ,  Tsuyoshi Tanaka

IPC: H01L21/00 ,  H01L29/06 ,  H01L31/072

CPC classification number: H01L27/0605 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A semiconductor device includes a semiconductor substrate of n-type silicon including, in an upper portion thereof, a first polarity inversion region and a second polarity inversion regions spaced from each other and doped with a p-type impurity. A first HFET including a first active layer and a second HFET including a second active layer both made of a group III-V nitride semiconductor are independently formed on the respective polarity inversion regions in the semiconductor substrate, and the HFETs are electrically connected to each other through interconnects.

Abstract translation: 半导体器件包括n型硅的半导体衬底，在其上部包括彼此间隔开并掺杂有p型杂质的第一极性反转区域和第二极性反转区域。 包括第一有源层的第一HFET和包括由III-V族氮化物半导体构成的第二有源层的第二HFET独立地形成在半导体衬底中的相应极性反转区域上，并且HFET彼此电连接 通过互连。

公开(公告)号：US20090301749A1

公开(公告)日：2009-12-10

申请号：US11915914

申请日：2007-02-13

Applicant: Tsuyoshi Tanaka ,  Masaharu Yamamoto

Inventor： Tsuyoshi Tanaka ,  Masaharu Yamamoto

IPC: H05K5/06 ,  B44C1/22 ,  B23K1/20

CPC classification number: H01L23/10 ,  H01L21/4817 ,  H01L23/06 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1617 ,  H01L2924/16195 ,  H01L2924/1627

Abstract: A hermetic sealing cap can be provided which is capable of suppressing that a production process becomes complicated, and additionally of suppressing that a solder layer wetly spreads inward on a sealing surface. This hermetic sealing cap (1, 30) includes a base member (2), a first plating layer (3, 31) that is formed on the surface of the base member, and a second plating layer (4, 32) that is formed on the surface of the first plating layer and is less oxidized than the first plating layer, wherein a part of the second plating layer in an area (S1, S5) inside an area (S2, S6) to which an electronic component accommodation member is joined is removed so that the surface of the first plating layer is exposed, and the surface of the first plating layer that is exposed in the area from which the second plating layer is removed is oxidized.

Abstract translation: 可以提供一种能够抑制生产过程变得复杂的气密密封盖，另外抑制焊料层在密封表面上向内湿润地扩展。 该气密密封盖（1,30）包括基体（2），形成在基体表面上的第一镀层（3,31）和形成的第二镀层（4,32） 在第一镀层的表面上比第一镀层氧化少，其中在电子部件容纳部件的区域（S2，S6）内的区域（S1，S5）内的区域（S1，S5）中的部分第二镀层 被除去，使得第一镀层的表面被暴露，并且暴露在从其去除第二镀层的区域中的第一镀层的表面被氧化。

公开(公告)号：US07612426B2

公开(公告)日：2009-11-03

申请号：US11272878

申请日：2005-11-15

Applicant: Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L29/872

CPC classification number: H01L29/872 ,  H01L21/26506 ,  H01L27/0605 ,  H01L27/0814 ,  H01L29/0692 ,  H01L29/417 ,  H01L29/66143

Abstract: A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a semiconductor substrate with a buffer layer formed between the first and second semiconductor layers and the semiconductor substrate. A Schottky electrode and an ohmic electrode spaced from each other are formed on the second semiconductor layer, and a back face electrode is formed on the back face of the semiconductor substrate. The Schottky electrode or the ohmic electrode is electrically connected to the back face electrode through a via penetrating through at least the buffer layer.

Abstract translation: 肖特基势垒二极管包括在半导体衬底上连续形成的第一半导体层和形成在第一和第二半导体层与半导体衬底之间的缓冲层的第二半导体层。 在第二半导体层上形成有彼此间隔开的肖特基电极和欧姆电极，在半导体基板的背面形成背面电极。 肖特基电极或欧姆电极通过贯穿至少缓冲层的通孔电连接到背面电极。

公开(公告)号：US07605441B2

公开(公告)日：2009-10-20

申请号：US11730422

申请日：2007-04-02

Applicant: Kazushi Nakazawa ,  Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

Inventor： Kazushi Nakazawa ,  Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC: H01L27/095 ,  H01L21/28 ,  H01L29/47

CPC classification number: H01L29/872 ,  H01L29/2003 ,  H01L29/66212

Abstract: A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.

Abstract translation: 半导体器件包括：由III族氮化物半导体制成并具有与第一表面相对的第一表面和第二表面的半导体层; 形成在半导体层的第一表面上的肖特基电极; 以及与半导体层的第二表面电连接的欧姆电极。 半导体层至少在其上部具有选择性地形成为具有高电阻的高电阻区域。

公开(公告)号：US07553747B2

公开(公告)日：2009-06-30

申请号：US11495454

申请日：2006-07-31

Applicant: Yutaka Hirose ,  Tsuyoshi Tanaka

Inventor： Yutaka Hirose ,  Tsuyoshi Tanaka

IPC: H01L29/74

CPC classification number: H01L29/872 ,  H01L29/2003 ,  H01L29/66143

Abstract: A Schottky diode includes a first nitride semiconductor layer formed on a substrate and a second nitride semiconductor layer selectively formed on the first nitride semiconductor layer and having a different conductivity type from that of the first nitride semiconductor layer. A Schottky electrode is selectively formed on the first nitride semiconductor layer to come into contact with the top surface of the second nitride semiconductor layer, and an ohmic electrode is formed thereon so as to be spaced apart from the Schottky electrode.

Abstract translation: 肖特基二极管包括形成在衬底上的第一氮化物半导体层和选择性地形成在第一氮化物半导体层上并且具有与第一氮化物半导体层的导电类型不同的导电类型的第二氮化物半导体层。 肖特基电极选择性地形成在第一氮化物半导体层上以与第二氮化物半导体层的顶表面接触，并且在其上形成欧姆电极以与肖特基电极间隔开。

公开(公告)号：US20090140994A1

公开(公告)日：2009-06-04

申请号：US12269447

申请日：2008-11-12

Applicant: Tsuyoshi Tanaka ,  Hitokazu Shitanaka ,  Kouichi Santo

Inventor： Tsuyoshi Tanaka ,  Hitokazu Shitanaka ,  Kouichi Santo

IPC: G06F3/041

CPC classification number: H01H13/83 ,  H01H2003/0293 ,  H01H2217/032 ,  H01H2219/039 ,  H01H2219/064 ,  H01H2221/016 ,  H01H2231/026 ,  H01H2239/006

Abstract: An input apparatus includes: a display plate having a plurality of display sections; an electrostatic touch panel provided at a lower face of the display plate; an operation body on which the display plate and the electrostatic touch panel are placed; a plurality of light-emitting elements for illuminating the plurality of display sections of the display plate from a lower side of the display plate through the electrostatic touch panel; and a control section that is electrically connected to the electrostatic touch panel and the plurality of light-emitting elements, and that controls light emission of the plurality of light-emitting elements in accordance with touch operation to the electrostatic touch panel.

Abstract translation: 输入装置包括：显示板，具有多个显示部分; 设置在所述显示板的下表面的静电触摸面板; 其上放置有显示板和静电式触摸面板的操作体; 多个发光元件，用于通过静电触摸面板从显示板的下侧照亮显示板的多个显示部分; 以及控制部分，其电连接到静电触摸面板和多个发光元件，并且根据对静电触摸面板的触摸操作来控制多个发光元件的发光。

公开(公告)号：US20090121775A1

公开(公告)日：2009-05-14

申请号：US11995040

申请日：2006-06-27

Applicant: Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Masahiro Hikita ,  Hiroaki Ueno

Inventor： Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Masahiro Hikita ,  Hiroaki Ueno

IPC: H01L29/207 ,  H03K17/687

CPC classification number: H01L29/739 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7786

Abstract: In a transistor, an AlN buffer layer 102, an undoped GaN layer 103, an undoped AlGaN layer 104, a p-type control layer 105, and a p-type contact layer 106 are formed in this order on a sapphire substrate 101. The transistor further includes a gate electrode 110 in ohmic contact with the p-type contact layer 106, and a source electrode 108 and a drain electrode 109 provided on the undoped AlGaN layer 104. By applying a positive voltage to the p-type control layer 105, holes are injected into a channel to increase a current flowing in the channel.

Abstract translation: 在晶体管中，在蓝宝石衬底101上依次形成AlN缓冲层102，未掺杂的GaN层103，未掺杂的AlGaN层104，p型控制层105和p型接触层106。 晶体管还包括与p型接触层106欧姆接触的栅电极110以及设置在未掺杂的AlGaN层104上的源电极108和漏极109.通过向p型控制层105施加正电压 ，孔被注入到通道中以增加在通道中流动的电流。

公开(公告)号：US20090050937A1

公开(公告)日：2009-02-26

申请号：US12257807

申请日：2008-10-24

Applicant: Tomohiro MURATA ,  Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

Inventor： Tomohiro MURATA ,  Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

IPC: H01L29/778

CPC classification number: H01L29/66871 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/8128

Abstract: A semiconductor device of the present invention includes: a III-V nitride semiconductor layer including a channel region in which carriers travel; a concave portion provided in an upper portion of the channel region in the III-V nitride semiconductor layer; and a Schottky electrode consisting of a conductive material forming a Schottky junction with the semiconductor layer, and formed on a semiconductor layer, which spreads over the concave portion and peripheral portions of the concave portion, on the III-V nitride semiconductor layer. A dimension of the concave portion in a depth direction is set so that a portion of the Schottky electrode provided in the concave portion can adjust a quantity of the carriers traveling in the channel region.

Abstract translation: 本发明的半导体器件包括：III-V族氮化物半导体层，其包括载流子行进的沟道区; 设置在III-V族氮化物半导体层中的沟道区的上部的凹部; 和由形成与半导体层形成肖特基结的导电材料构成的肖特基电极，形成在III-V族氮化物半导体层上的在凹部的凹部和周边部分上方扩散的半导体层上。 深度方向上的凹部的尺寸被设定为使得设置在凹部中的肖特基电极的一部分可以调节在沟道区域中行进的载流子的量。

公开(公告)号：US20080287319A1

公开(公告)日：2008-11-20

申请号：US11816575

申请日：2006-02-27

Applicant: Tadashi Matsunaga ,  Haruko Takeyama ,  Tsuyoshi Tanaka ,  Takeo Tanaami ,  Saya Sato ,  Hisao Katakura ,  Yuji Mitsumori ,  Takeyuki Mogi

Inventor： Tadashi Matsunaga ,  Haruko Takeyama ,  Tsuyoshi Tanaka ,  Takeo Tanaami ,  Saya Sato ,  Hisao Katakura ,  Yuji Mitsumori ,  Takeyuki Mogi

IPC: C40B40/08 ,  C07H1/00

CPC classification number: C12N15/1006 ,  C12Q1/6806 ,  C12Q1/6837 ,  C12Q2563/131 ,  C12Q2523/113

Abstract: A separation method of single-stranded nucleic acid characterized in that nucleic acid amplification is performed using a first primer to which a second substance capable of binding specifically to a first substance is bound and a second primer to which the second substance is not bound, and double-stranded nucleic acid obtained by the nucleic acid amplification is bound to the first substance, and the double-stranded nucleic acid bound to the first substance is dissociated into a single strand, and a separation apparatus of single-stranded nucleic acid characterized by having a nucleic acid amplification part 1 for performing nucleic acid amplification using a first primer to which a second substance capable of binding specifically to a first substance is bound and a second primer to which the second substance is not bound, a binding part 2 for binding double-stranded nucleic acid obtained by the nucleic acid amplification to the first substance, and a dissociation part 3 for dissociating the double-stranded nucleic acid bound to the first substance into a single strand.

Abstract translation: 单链核酸的分离方法，其特征在于，使用与第一物质结合的能够结合第二物质的第一物质与第二物质不结合的第二引物的第一引物进行核酸扩增， 通过核酸扩增获得的双链核酸与第一物质结合，将与第一物质结合的双链核酸解离为单链，单链核酸的分离装置的特征在于，具有 用于使用与第一物质结合特异性的第二物质结合的第一引物和第二物质不结合的第二引物进行核酸扩增的核酸扩增部分1，用于结合双重结合部分2 通过对第一物质进行核酸扩增获得的品种核酸，以及用于dissocia的解离部分3 将与第一物质结合的双链核酸结合成单链。