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31.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的位交换机检查长度为16200，编码速率为4/15和256符号映射，以及使用相同的位交互方法公开(公告)号：US20160241269A1
公开(公告)日：2016-08-18
申请号：US14718839
申请日：2015-05-21
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/1165 , H03M13/255 , H03M13/2778
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为16200且码率为4/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于256符号映射的调制器。
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公开(公告)号：US20160218908A1
公开(公告)日：2016-07-28
申请号：US15008268
申请日：2016-01-27
Inventor： Myung-Sun BAEK , Hyoungsoo LIM , Sang-Woon KWAK , Young-Su KIM , Yun-Jeong SONG , Kyu-Tae YANG , Joungil YUN , Bongho LEE , Jong-Suk CHAE , Nam-Ho HUR
CPC classification number: H04B1/713 , H04J11/0023 , H04L5/0012
Abstract: Provided is an apparatus for transmitting a signal based on a non-uniform inter-symbol interference (ISI) pattern, the apparatus that may transmit an output signal generated by modulating an input signal based on a parameter sequence to be used to control an interference pattern and a position of a transmission signal for each symbol using a faster than Nyquist (FTN) scheme.
Abstract translation: 提供了一种用于基于不均匀的符号间干扰（ISI）模式发送信号的装置，该装置可以基于要用于控制干扰模式的参数序列来发送通过调制输入信号而产生的输出信号 以及使用比奈奎斯特（FTN）方案快的每个符号的发送信号的位置。
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33.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的位交换机检查长度为16200，编码速率为2/15和64符号映射，以及使用相同的位交互方法公开(公告)号：US20160218746A1
公开(公告)日：2016-07-28
申请号：US14718013
申请日：2015-05-20
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2767 , H03M13/1165 , H03M13/255 , H03M13/2778 , H03M13/2792 , H04L1/0057 , H04L1/0071 , H04L2001/0093
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为16200且码率为2/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于64符号映射的调制器。
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34.发明申请LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME 有权低密度奇偶校验编码器的长度为64800，编码速率为2/15，低密度奇偶校验编码方法使用该编码方法公开(公告)号：US20160049957A1
公开(公告)日：2016-02-18
申请号：US14496457
申请日：2014-09-25
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
CPC classification number: H03M13/1177 , H03M13/1102 , H03M13/1105 , H03M13/116 , H03M13/1165 , H03M13/1185 , H03M13/255 , H03M13/616 , H03M13/6552 , H04L1/0057
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Abstract translation: 公开了一种低密度奇偶校验（LDPC）编码器，LDPC解码器和LDPC编码方法。 LDPC编码器包括第一存储器，第二存储器和处理器。 第一存储器存储长度为64800，码率为2/15的LDPC码字。 第二存储器被初始化为0.处理器通过使用与奇偶校验矩阵（PCM）相对应的序列执行相对于第二存储器的累积来生成与信息位对应的LDPC码字。
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公开(公告)号：US20240162918A1
公开(公告)日：2024-05-16
申请号：US18419393
申请日：2024-01-22
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
CPC classification number: H03M13/1157 , H03M13/1165 , H03M13/1177 , H03M13/616 , H03M13/618
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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Patent Agency Ranking
公开(公告)号：US20230268935A1
公开(公告)日：2023-08-24
申请号：US18309278
申请日：2023-04-28
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2757 , H04L27/20 , H03M13/2792 , H04L27/3416 , H03M13/255 , H04L1/0057 , H04L1/0071 , H03M13/116 , H03M13/1185 , H03M13/2778 , H03M13/1102 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0058
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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37.发明公开公开(公告)号：US20230155634A1
公开(公告)日：2023-05-18
申请号：US17859969
申请日：2022-07-07
Inventor： Bo-Mi LIM , Hoi-Yoon JUNG , Sung-Ik PARK , Hae-Chan KWON , Sung-Jun AHN , Nam-Ho HUR , Hyun-Jeong YIM
IPC: H04B7/0413 , H04W4/06 , H04L1/00
CPC classification number: H04B7/0413 , H04W4/06 , H04L1/0071
Abstract: Disclosed herein are a method for transmitting a broadcast signal for signaling information about a combination of Layered-Division Multiplexing (LDM) technology and Multiple-Input Multiple-Output (MIMO) technology and an apparatus using the method. The method includes generating first signaling information indicating whether MIMO technology is applied to an enhanced layer by LDM technology, generating second signaling information indicating an MIMO application method when the MIMO technology is applied to the enhanced layer, and generating a broadcast signal using the first signaling information and the second signaling information.
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公开(公告)号：US20220360282A1
公开(公告)日：2022-11-10
申请号：US17864144
申请日：2022-07-13
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号：US20220302927A1
公开(公告)日：2022-09-22
申请号：US17835651
申请日：2022-06-08
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号：US20220216931A1
公开(公告)日：2022-07-07
申请号：US17700751
申请日：2022-03-22
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
IPC: H04H20/67 , H04H20/71 , H04L1/00 , H04L69/323 , H04L27/26 , H04H20/31 , H04H60/44 , H04J11/00 , H04H60/73 , H04W52/32
Abstract: An apparatus for transmitting broadcasting signal using transmitter identification scaled by 4-bit injection level code and method using the same are disclosed. An apparatus for transmitting broadcasting signal according to an embodiment of the present invention includes a waveform generator configured to generate a host broadcasting signal; a transmitter identification signal generator configured to generate a transmitter identification signal for identifying a transmitter, the transmitter identification signal scaled by an injection level code; and a combiner configured to inject the transmitter identification signal into the host broadcasting signal in a time domain so that the transmitter identification signal is transmitted synchronously with the host broadcasting signal.
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