知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

166 records (took 0.034 seconds)

    Predictive, adaptive power supply for an integrated circuit under test
    32.
    发明授权
    Predictive, adaptive power supply for an integrated circuit under test 有权
    用于被测集成电路的预测，自适应电源

    公开(公告)号：US07714603B2

    公开(公告)日：2010-05-11

    申请号：US11779188

    申请日：2007-07-17

    Applicant: Benjamin N. Eldridge ,  Charles A. Miller

    Inventor： Benjamin N. Eldridge ,  Charles A. Miller

    IPC: G01R31/26 ,  G01R31/36

    CPC classification number: G06F1/26 ,  G01R31/2851 ,  G01R31/31721 ,  G01R31/31905 ,  G01R31/31924

    Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.

    Abstract translation: 主电源将电流通过路径阻抗提供给被测集成电路器件（DUT）的电源端子。 在测试期间，DUT对电源输入端的电流需求暂时增加了在测试期间施加到DUT的时钟信号的随后边缘，作为IC开关中的晶体管响应于时钟信号的边缘。 为了限制电源输入端子的电压变化（噪声），辅助电源为电源输入端子提供额外的电流脉冲，以满足在时钟信号的每个周期期间增加的需求。 电流脉冲的大小是在该时钟周期期间电流需求的预测增加以及由反馈电路控制的适配信号的大小的函数，以限制在DUT的功率输入端产生的电压变化。

    Test method for yielding a known good die
    33.
    发明授权
    Test method for yielding a known good die 有权
    用于产生已知好的模具的测试方法

    公开(公告)号：US07694246B2

    公开(公告)日：2010-04-06

    申请号：US10177367

    申请日：2002-06-19

    Applicant: Charles A. Miller ,  Timothy E. Cooper ,  Yoshikazu Hatsukano

    Inventor： Charles A. Miller ,  Timothy E. Cooper ,  Yoshikazu Hatsukano

    IPC: G06F17/50

    CPC classification number: G11C29/56 ,  G01R31/2831 ,  G01R31/2886 ,  G01R31/31718 ,  G11C29/006 ,  G11C29/56016

    Abstract: A semiconductor wafer is cut to singulate integrated circuit dice formed on the wafer. A die pick machine then positions and orients the singulated dice on a carrier base such that signal, power and ground pads formed on the surface of each die reside at predetermined positions relative to landmarks on the carrier base the die pick machine optically identifies. With the dice temporarily held in place on the carrier base, they are subjected to a series of testing and other processing steps. Since each die's signal pads reside in predetermined locations, they can be accessed by appropriately arranged probes providing test equipment with signal access to the pads during tests. After each test, a die pick machine may replace any die that fails the test with another die, thereby improving efficiency of subsequent testing and other processing resources.

    Abstract translation: 切割半导体晶片以对形成在晶片上的集成电路芯片进行分割。 然后，骰子拾取机器将分离的骰子定位和定位在载体基座上，使得形成在每个模具表面上的信号，功率和接地垫相对于骰子拾取机器光学识别的载体基座上的标志位于预定位置。 将骰子临时固定在承运人基地上，对其进行一系列测试和其他处理步骤。 由于每个管芯的信号焊盘都位于预定位置，所以它们可以通过适当布置的探头进行访问，从而在测试期间为测试设备提供对焊盘的信号访问。 在每次测试之后，模具拾取机器可以用另一个模具代替未测试的任何模具，从而提高后续测试和其他处理资源的效率。

    Adjustable delay transmission line
    34.
    发明授权
    Adjustable delay transmission line 有权
    可调延时传输线

    公开(公告)号：US07683738B2

    公开(公告)日：2010-03-23

    申请号：US11773011

    申请日：2007-07-03

    Applicant: Charles A. Miller

    Inventor： Charles A. Miller

    IPC: H01P9/00

    CPC classification number: H01P9/00 ,  G01R31/2822

    Abstract: A transmission line includes a signal conductor and at least one varactor diode capacitively coupled to the signal conductor. The transmission line's signal path delay is a function of its shunt capacitance, and the varactor's capacitance forms a part of the transmission line's shunt capacitance. The transmission line's signal path delay is adjusted by adjusting a control voltage across the varactor diode thereby to adjust the varactor diode's capacitance.

    Abstract translation: 传输线包括电容耦合到信号导体的信号导体和至少一个变容二极管。 传输线的信号路径延迟是其分流电容的函数，变容二极管的电容构成传输线分流电容的一部分。 通过调整变容二极管两端的控制电压来调整传输线的信号路径延迟，从而调整变容二极管的电容。

    Contactless interfacing of test signals with a device under test
    36.
    发明授权
    Contactless interfacing of test signals with a device under test 失效
    测试信号与被测器件的非接触式接口

    公开(公告)号：US07466157B2

    公开(公告)日：2008-12-16

    申请号：US10772970

    申请日：2004-02-05

    Applicant: Charles A. Miller

    Inventor： Charles A. Miller

    IPC: G01R31/28 ,  G01R31/303

    CPC classification number: G01R1/0491 ,  G01R1/07 ,  G01R1/07378 ,  G01R31/3025

    Abstract: An interface device receives test data from a tester. A signal representing the test data is transmitted to a device under test through electromagnetically coupled structures on the interface device and the device under test. The device under test processes the test data and generates response data. A signal representing the response data is transmitted to the interface device through electromagnetically coupled structures on the device under test and the interface device.

    Abstract translation: 接口设备从测试器接收测试数据。 表示测试数据的信号通过接口设备和被测设备上的电磁耦合结构发送到被测设备。 被测设备处理测试数据并产生响应数据。 表示响应数据的信号通过被测设备和接口设备上的电磁耦合结构传送到接口设备。

    High performance probe system
    37.
    发明授权
    High performance probe system 有权
    高性能探头系统

    公开(公告)号：US07443181B2

    公开(公告)日：2008-10-28

    申请号：US11758525

    申请日：2007-06-05

    Applicant: Charles A. Miller

    Inventor： Charles A. Miller

    IPC: G01R31/02

    CPC classification number: G01R31/2889 ,  G01R1/07314 ,  G01R1/07378 ,  G01R31/31905 ,  Y10T29/49117

    Abstract: A probe system for providing signal paths between an integrated circuit (IC) tester and input/output, power and ground pads on the surfaces of ICs to be tested includes a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I/O pads. The probe board assembly includes one or more rigid substrate layers with traces and vias formed on or within the substrate layers providing relatively low bandwidth signal paths linking the tester to probes accessing some of the IC's pads. The flex cable provides relatively high bandwidth signal paths linking the tester to probes accessing others of the IC's pads.

    Abstract translation: 用于在集成电路（IC）测试器和要测试的IC的表面上的输入/输出，电源和接地焊盘之间提供信号路径的探针系统包括探针板组件，柔性电缆和一组探针， IC的I / O焊盘。 探针板组件包括一个或多个刚性衬底层，其具有形成在衬底层上或衬底层内的迹线和通孔，其提供将测试器连接到访问IC的一些衬垫的探针的相对低带宽的信号路径。 柔性电缆提供相对高带宽的信号路径，将测试仪连接到访问IC其他焊盘的探针。

    Apparatus for reducing power supply noise in an integrated circuit
    38.
    发明授权
    Apparatus for reducing power supply noise in an integrated circuit 有权
    用于降低集成电路中电源噪声的装置

    公开(公告)号：US07342405B2

    公开(公告)日：2008-03-11

    申请号：US10062999

    申请日：2002-01-30

    Applicant: Benjamin N. Eldridge ,  Charles A. Miller

    Inventor： Benjamin N. Eldridge ,  Charles A. Miller

    IPC: G01R31/26

    CPC classification number: G01R31/31721 ,  G01R31/2851 ,  G01R31/31905 ,  G01R31/31924 ,  G06F1/26

    Abstract: A power supply provides power to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal may temporarily increase due, for example, to state changes in the DUT. To limit variation (noise) in voltage at the power input terminal, a supplemental current is supplied to the power input terminal.

    Abstract translation: 电源为被测集成电路设备（DUT）的电源端子供电。 DUT在电源输入端子上对电流的需求可能由于例如DUT的状态变化而暂时增加。 为了限制电源输入端子电压的变化（噪声），补充电流被提供给电源输入端子。

    Bi-directional buffer for interfacing test system channel
    39.
    发明授权
    Bi-directional buffer for interfacing test system channel 有权
    用于接口测试系统通道的双向缓冲器

    公开(公告)号：US07262624B2

    公开(公告)日：2007-08-28

    申请号：US11018211

    申请日：2004-12-21

    Applicant: Charles A. Miller

    Inventor： Charles A. Miller

    IPC: G01R31/26

    CPC classification number: G01R31/2889 ,  G01R31/31713

    Abstract: An emitter follower or source follower transistor is provided in the channel of a wafer test system between a DUT and a test system controller to enable a low power DUT to drive a test system channel. A bypass resistor is included between the base and emitter of the emitter follower transistor to enable bi-directional signals to be provided between the DUT channel and test system controller, as well as to enable parametric tests to be performed. The emitter follower transistor and bypass resistor can be provided on the probe card, with a pull down termination circuit included in the test system controller. The test system controller can provide compensation for the base to emitter voltage drop of the emitter follower transistor.

    Abstract translation: 在DUT和测试系统控制器之间的晶片测试系统的通道中提供射极跟随器或源极跟随器晶体管，以使低功率DUT能够驱动测试系统通道。 在射极跟随器晶体管的基极和发射极之间包括一个旁路电阻，以便能够在DUT通道和测试系统控制器之间提供双向信号，以及执行参数测试。 射极跟随器晶体管和旁路电阻可以在探针卡上提供，测试系统控制器中包含一个下拉终端电路。 测试系统控制器可以为射极跟随器晶体管的基极到发射极电压降提供补偿。

Patent Agency Ranking