Heterojunction bipolar transistor and integration of same with field
effect device
    33.
    发明授权
    Heterojunction bipolar transistor and integration of same with field effect device 失效
    异质结双极晶体管和与场效应器件的集成

    公开(公告)号:US5097312A

    公开(公告)日:1992-03-17

    申请号:US701570

    申请日:1991-05-14

    IPC分类号: H01L27/06

    摘要: An integrated circuit including both bipolar and field effect devices is disclosed, comprising a first continuous layer 102/104 of semi-insulating semiconductor material having a continuous first surface, a doped channel region 108 in the first layer 102/104 at the first surface of the first layer 102/104, a doped collector region 114 in the first layer 102/104 at the first surface spaced from the channel region 108, a doped base layer 122 on the collector region 114, the base layer 122 of conductivity type opposite that of the collector region 114, a doped emitter region 124 on the base layer 122, the emitter region 124 of the same conductivity type as the collector 114 to provide a bipolar device, the emitter region 124 made of semiconductor material with a wider bandgap than the base layer 122 semiconductor material, source and drain contacts 138 on the channel region 108, a gate 146 on the channel region 108 between the source and drain contacts 138 to provide a field effect device, and electrical coupling between at least one of the emitter 124, base 122 and collector 114 of the bipolar device and at least one of the gate 146, source and drain 138 of the field effect device. Other devices, systems and methods are also disclosed.

    摘要翻译: 公开了一种包括双极和场效应器件的集成电路,其包括具有连续第一表面的半绝缘半导体材料的第一连续层102/104,在第一表面102/104处的第一层102/104中的掺杂沟道区108 第一层102/104,在与沟道区108间隔开的第一表面处的第一层102/104中的掺杂集电极区域114,集电区域114上的掺杂基极层122,导电类型的基极层122与 的集电极区域114,基极层122上的掺杂发射极区域124,与集电极114相同导电类型的发射极区域124以提供双极器件,由半导体材料制成的发射极区域124具有比 基极层122半导体材料,沟道区域108上的源极和漏极触点138,在源极和漏极触点138之间的沟道区域108上的栅极146,以提供场效应器件 以及双极器件的发射极124,基极122和集电极114中的至少一个与场效应器件的栅极146,源极和漏极138中的至少一个之间的电耦合。 还公开了其他装置,系统和方法。

    Anodizing a compound semiconductor
    34.
    发明授权
    Anodizing a compound semiconductor 失效
    阳极氧化化合物半导体

    公开(公告)号:US4133724A

    公开(公告)日:1979-01-09

    申请号:US856094

    申请日:1977-11-30

    摘要: A method of anodizing a compound semiconductor comprises(1) plating a metal on the compound semiconductor,(2) contacting the exposed surface of the metal with an electrolyte which permits anodic oxidation of the metal, and(3) passing an electric current through the electrolyte with the exposed surface of the metal acting as an anode, the current density not exceeding 100 microamps per square centimeter of the surface and the quantity of current being more than sufficient to oxidize anodically all the metal.

    摘要翻译: 阳极氧化化合物半导体的方法包括(1)在化合物半导体上镀金属,(2)用金属阳极氧化的电解质接触金属的暴露表面,以及(3)通过金属通过电流 以金属表面作为阳极的电解质,电流密度不超过100微米每平方厘米的表面和当前的数量超过任何非常阳离子氧化所有的金属。

    Termal shunt stabilization of multiple part heterojunction bipolar
transistors
    35.
    发明授权
    Termal shunt stabilization of multiple part heterojunction bipolar transistors 失效
    多部分异质结双极晶体管的分流稳流

    公开(公告)号:US5734193A

    公开(公告)日:1998-03-31

    申请号:US521513

    申请日:1995-08-30

    摘要: Structure and fabrication details are disclosed for AlGaAs/GaAs microwave HBTs having improved thermal stability during high power operation. The use of a thermal shunt joining emitter contacts of a multi-emitter HBT is shown to improve this thermal stability and eliminate "current-crush" effects. A significant reduction in thermal resistance of the disclosed devices is also achieved by spreading the generated heat over a large substrate area using thermal lens techniques in the thermal shunt. These improvements achieve thermally stable operation of AlGaAs/GaAs HBTs up to their electronic limitations. A power density of 10 mW/.mu.m2 of emitter area is achieved with 0.6 W CW output power and 60% power-added efficiency at 10 GHz. The thermal stabilization technique is applicable to other bipolar transistors including silicon, germanium, and indium phosphide devices. The disclosed fabrication sequence employs an improved two-step polyimide electrical isolation planarization sequence in preparation for fabrication of the thermal shunting element.

    摘要翻译: 公开了在高功率操作期间具有改进的热稳定性的AlGaAs / GaAs微波HBT的结构和制造细节。 显示使用多发射极HBT的热分流连接发射极触点来改善这种热稳定性并消除“电流冲击”效应。 所公开的装置的热阻的显着降低也通过使用热分流中的热透镜技术在大的衬底区域上扩展所产生的热量来实现。 这些改进实现了AlGaAs / GaAs HBT的热稳定运行,达到其电子限制。 发射极面积为10 mW / m 2,功率密度为0.6 W CW输出功率,60 GHz功率附加效率达到10 GHz。 该热稳定技术适用于包括硅,锗和磷化铟装置在内的其它双极晶体管。 所公开的制造顺序采用改进的两步聚酰亚胺电隔离平面化顺序来制备热分流元件。

    Circuit integrating heterojunction bipolar transistors with pin diodes
    37.
    发明授权
    Circuit integrating heterojunction bipolar transistors with pin diodes 失效
    异步双极晶体管与引脚二极管的集成电路

    公开(公告)号:US5401999A

    公开(公告)日:1995-03-28

    申请号:US15755

    申请日:1993-02-10

    CPC分类号: H01L27/0605

    摘要: Generally, and in one form of the invention, a semi-insulating semiconductor substrate 10 is provided having a first surface. An HBT subcollector region 12 of a first conductivity type is implanted in the substrate 10 at the first surface. A PIN diode region 14 of the first conductivity type is then implanted in the substrate 10 at the first surface and spaced from the HBT subcollector region 12. Next, an i-layer 16 is grown over the first surface. Next, an HBT base/PIN diode layer 22 of a second conductivity type is selectively grown on the i-layer 16 over the HBT subcollector region 12 and the PIN diode region 14. Then, an HBT emitter layer 24/26/28 of the first conductivity type is selectively grown over the HBT base/PIN diode layer 22, the HBT emitter layer 24/26/28 having a wider energy bandgap than the HBT base/PIN diode layer 22. Afterwards, an isolation region 30 is implanted at the boundary between the HBT subcollector region 12 and the PIN diode region 14, the isolation region 30 extending down into the substrate 10. Next, the HBT emitter layer 24/26/28 is etched away over the PIN diode region 14. Lastly, conductive contacts 32, 36, 40, 38 and 42 are formed to the HBT emitter layer 24/26/28, the HBT base layer 22, the HBT subcollector region 12, the PIN diode layer 22 and the PIN diode region 14.Other devices, systems and methods are also disclosed.

    摘要翻译: 通常,在本发明的一种形式中,提供具有第一表面的半绝缘半导体衬底10。 第一导电类型的HBT子集电极区域12在第一表面被注入到衬底10中。 然后将第一导电类型的PIN二极管区域14在第一表面处注入衬底10中并与HBT子集电极区域12间隔开。接下来,在第一表面上生长i层16。 接下来,在HBT子集电极区域12和PIN二极管区域14上,在i层16上选择性地生长第二导电类型的HBT基极/ PIN二极管层22.然后,HBT发射极层24/26/28 第一导电类型选择性地生长在HBT基极/ PIN二极管层22上,HBT发射极层24/26/28具有比HBT基极/ PIN二极管层22更宽的能量带隙。之后,隔离区域30被植入 HBT子集电极区域12和PIN二极管区域14之间的边界,隔离区域30向下延伸到衬底10中。接下来,在PIN二极管区域14上蚀刻掉HBT发射极层24/26/28。最后,导电触点 32,36,40,38和42形成于HBT发射极层24/26/28,HBT基极层22,HBT子集电极区12,PIN二极管层22和PIN二极管区14.其它器件,系统 并且还公开了方法。

    P-N junction diffusion barrier employing mixed dopants
    38.
    发明授权
    P-N junction diffusion barrier employing mixed dopants 失效
    采用混合掺杂剂的P-N结扩散势垒

    公开(公告)号:US5387807A

    公开(公告)日:1995-02-07

    申请号:US969666

    申请日:1992-10-30

    摘要: Generally, and in one form of the invention, a p-n junction diffusion barrier is disclosed comprising a first semiconductor layer 28 of p-type conductivity, a second semiconductor layer 32 of n-type conductivity and a third semiconductor layer 30 of p-type conductivity disposed between the first and second layers, the third layer being doped with a relatively low diffusivity dopant in order to form a diffusion barrier between the first and the second semiconductor layers.

    摘要翻译: 通常,在本发明的一种形式中,公开了一种pn结扩散阻挡层,其包括p型导电性的第一半导体层28,n型导电性的第二半导体层32和p型导电性的第三半导体层30 设置在第一和第二层之间,第三层掺杂有相对低的扩散性掺杂剂,以便在第一和第二半导体层之间形成扩散阻挡层。

    Method of integrating heterojunction bipolar transistors with PIN diodes
    40.
    发明授权
    Method of integrating heterojunction bipolar transistors with PIN diodes 失效
    异质结双极晶体管与PIN二极管的集成方法

    公开(公告)号:US5213987A

    公开(公告)日:1993-05-25

    申请号:US676419

    申请日:1991-03-28

    CPC分类号: H01L27/0605

    摘要: Generally, and in one form of the invention, a semi-insulating semiconductor substrate 10 is provided having a first surface. An HBT subcollector region 12 of a first conductivity type is implanted in the substrate 10 at the first surface. A PIN diode region 14 of the first conductivity type is then implanted in the substrate 10 at the first surface and spaced from the HBT subcollector region 12. Next, an i-layer 16 is grown over the first surface. Next, an HBT base/PIN diode layer 22 of a second conductivity type is selectively grown on the i-layer 16 over the HBT subcollector region 12 and the PIN diode region 14. Then, an HBT emitter layer 24/26/28 of the first conductivity type is selectively grown over the HBT base/PIN diode layer 22, the HBT emitter layer 24/26/28 having a wider energy bandgap than the HBT base/PIN diode layer 22. Afterwards, an isolation region 30 is implanted at the boundary between the HBT subcollector region 12 and the PIN diode region 14, the isolation region 30 extending down into the substrate 10. Next, the HBT emitter layer 24/26/28 is etched away over the PIN diode region 14. Lastly, conductive contacts 32, 36, 40, 38 and 42 are formed to the HBT emitter layer 24/26/28, the HBT base layer 22, the HBT subcollector region 12, the PIN diode layer 22 and the PIN diode region 14.

    摘要翻译: 通常,在本发明的一种形式中,提供具有第一表面的半绝缘半导体衬底10。 第一导电类型的HBT子集电极区域12在第一表面被注入到衬底10中。 然后将第一导电类型的PIN二极管区域14在第一表面处注入衬底10中并与HBT子集电极区域12间隔开。接下来,在第一表面上生长i层16。 接下来,在HBT子集电极区域12和PIN二极管区域14上的i层16上选择性地生长第二导电类型的HBT基极/ PIN二极管层22.然后,HBT发射极层24/26/28 第一导电类型选择性地生长在HBT基极/ PIN二极管层22上,HBT发射极层24/26/28具有比HBT基极/ PIN二极管层22更宽的能量带隙。之后,隔离区域30被植入 HBT子集电极区域12和PIN二极管区域14之间的边界,隔离区域30向下延伸到衬底10中。接下来,在PIN二极管区域14上蚀刻掉HBT发射极层24/26/28。最后,导电触点 32,36,40,38和42形成于HBT发射极层24/26/28,HBT基极层22,HBT子集电极区12,PIN二极管层22和PIN二极管区14。