公开(公告)号：US10475409B2

公开(公告)日：2019-11-12

申请号：US15796463

申请日：2017-10-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Mingfu Han ,  Xing Yao ,  Guangliang Shang ,  Haoliang Zheng ,  Seung-Woo Han ,  Jiha Kim ,  Lijun Yuan ,  Zhichong Wang

IPC: G11C19/00 ,  G09G3/36 ,  G06F3/041 ,  G11C19/28

Abstract: The present disclosure discloses a gate drive circuit, a display panel and a driving method for the gate drive circuit. The gate drive circuit includes a plurality of shift register units connected in cascade; and further includes: buffer units which are in a one-to-one correspondence with shift register units at all levels, and touch control switch units which are in a one-to-one correspondence with shift register units at even levels. Each buffer unit in the gate drive circuit can increase the holding time of the effective pulse signal output by the shift register unit at a corresponding level by one line before resetting, and the effective pulse signal output by a buffer unit at an even level under the control of a touch control unit and the effective pulse signal output by a buffer unit at an adjacent previous odd level are reset at the same time.

公开(公告)号：US10317758B2

公开(公告)日：2019-06-11

申请号：US14409217

申请日：2014-06-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xing Yao

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1339 ,  G02F1/1368

Abstract: An array substrate and a display device having the array substrate are provided. The array substrate comprises a display region and a non-display region disposed at the periphery of the display region. The non-display region comprises a gate driver region (GOA region), which comprises a first patterned metal layer formed on a base substrate, a first insulating layer formed on the first patterned metal layer, a second patterned metal layer formed on the first insulating layer, a second insulating layer covering the second patterned metal layer, and a third patterned metal layer formed at a side of the second insulating layer away from the base substrate. The third patterned metal layer comprises a plurality of metal wires insulated from each other and connected to the first patterned metal layer and the second patterned metal layer respectively by through holes and used as connecting lines between elements of the gate driver.

公开(公告)号：US10269290B2

公开(公告)日：2019-04-23

申请号：US15680416

申请日：2017-08-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Mingfu Han ,  Haoliang Zheng ,  Han-Seung- Woo ,  Im-Yun- Sik ,  Jing Lv ,  Yinglong Huang ,  Jun-Jung- Mok ,  Xue Dong ,  Zhichong Wang ,  Xing Yao ,  Lijun Yuan ,  Zhihe Jin

IPC: G09G3/36 ,  G09G3/20 ,  G11C19/28 ,  G09G3/3266

Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.

公开(公告)号：US20180301200A1

公开(公告)日：2018-10-18

申请号：US15520191

申请日：2016-11-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Seungwoo Han ,  Mingfu Han ,  Haoliang Zheng ,  Xing Yao ,  Hyunsic Choi

IPC: G11C19/28 ,  G09G3/36

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/06 ,  G09G2310/08 ,  G09G2330/06

Abstract: The present application discloses a control circuit for controlling a noise reduction thin film transistor in a shift register unit. The control circuit includes a timer for initiating a timing process when the shift register is turned on, to obtain an operating time of the shift register; a threshold voltage calculator coupled to the timer for calculating a present threshold voltage based on the operating time, a gate voltage of the noise reduction thin film transistor, and an initial threshold voltage of the noise reduction thin film transistor; and a gate voltage controller coupled to the threshold voltage calculator for adjusting the gate voltage of the noise reduction thin film transistor during the noise reduction phase, to control the noise reduction thin film transistor in an ON state during the noise reduction phase.

公开(公告)号：US10096374B2

公开(公告)日：2018-10-09

申请号：US15539220

申请日：2016-11-01

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Seungwoo Han ,  Haoliang Zheng ,  Xing Yao ,  Mingfu Han ,  Hyunsic Choi ,  Yunsik Im ,  Yinglong Huang ,  Jungmok Jun ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/20

Abstract: The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.

公开(公告)号：US20180190180A1

公开(公告)日：2018-07-05

申请号：US15680416

申请日：2017-08-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Mingfu Han ,  Haoliang Zheng ,  Han-Seung- Woo ,  Im-Yun- Sik ,  Jing Lv ,  Yinglong Huang ,  Jun-Jung- Mok ,  Xue Dong ,  Zhichong Wang ,  Xing Yao ,  Lijun Yuan ,  Zhihe Jin

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G09G3/2092 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/043 ,  G09G2330/02 ,  G11C19/28

Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.

公开(公告)号：US10002675B2

公开(公告)日：2018-06-19

申请号：US15504119

申请日：2016-08-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang Zheng ,  Seungwoo Han ,  Xing Yao ,  Hyunsic Choi ,  Guangliang Shang ,  Mingfu Han ,  Yunsik Im ,  Jungmok Jun ,  Xue Dong

IPC: G09G5/00 ,  G11C19/28 ,  G09G3/36 ,  G11C19/18 ,  H01L27/12

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251

Abstract: The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.

公开(公告)号：US09524686B2

公开(公告)日：2016-12-20

申请号：US14436932

申请日：2014-07-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yuanbo Zhang ,  Jiayang Zhao ,  Seung Woo Han ,  Xing Yao ,  Haifeng Jin

IPC: G09G3/36 ,  G11C19/00 ,  G06F3/041 ,  G11C19/28

CPC classification number: G09G3/3648 ,  G06F3/0416 ,  G09G3/36 ,  G09G3/3674 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/00 ,  G11C19/28 ,  G11C19/287

Abstract: The present disclosure provides a shift register unit, a gate electrode drive circuit and a display apparatus, which relates to a technical field of display. The shift register unit includes an input reset module, a pull up module, a control module and a pull down module. By inputting a high level into the second signal input end of the input reset module in the touch scan to maintain the level at the pull up control node, the electrical leak effects at the pull up control node may be avoided efficiently. In this way, the defects of insufficient charging rate of the row pixels may be avoided and the dark lines or bad bright lines may be suppressed.

Abstract translation: 本公开提供了一种与显示技术领域有关的移位寄存器单元，栅电极驱动电路和显示装置。 移位寄存器单元包括输入复位模块，上拉模块，控制模块和下拉模块。 通过在触摸扫描中将高电平输入到输入复位模块的第二信号输入端以维持上拉控制节点处的电平，可以有效地避免上拉控制节点处的电泄漏效应。 以这种方式，可以避免行像素充电速率不足的缺陷，并且可以抑制暗线或不良亮线。

公开(公告)号：US20250124876A1

公开(公告)日：2025-04-17

申请号：US18577444

申请日：2023-03-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chengyuan Luo ,  Pan Xu ,  Ying Han ,  Donghui Zhao ,  Guangshuang Lv ,  Xing Zhang ,  Miao Liu ,  Xing Yao ,  Cheng Xu

IPC: G09G3/3266 ,  H10K59/131

Abstract: The present disclosure provides a circuitry structure and a display substrate. The circuitry structure includes a base substrate, and a functional transistor and a signal transmission line arranged on the base substrate. The functional transistor includes a first conductive connection member, a first electrode, a second electrode, at least two gate electrode patterns and at least one active pattern. Orthogonal projections of the first electrode, the second electrode and the at least two gate electrode patterns onto the base substrate at least partially overlap with an orthogonal projection of the active pattern onto the base substrate, and first ends of the gate electrode patterns are coupled to each other. The first conductive connection member is arranged at a layer different from the gate electrode pattern, and coupled to second ends of the gate electrode patterns. The signal transmission line is coupled to the first conductive connection member.

公开(公告)号：US12249279B2

公开(公告)日：2025-03-11

申请号：US18027376

申请日：2022-05-12

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Jiangnan Lu ,  Li Wang ,  Mengyang Wen ,  Xing Yao ,  Libin Liu

IPC: G09G3/3233 ,  G09G3/3266 ,  G09G3/3275

Abstract: Provided is a display substrate, a drive method thereof and a display apparatus, the display substrate includes: a first drive mode and a second drive mode, the first drive mode has a refresh rate less than that of the second drive mode, wherein the contents displayed on the display substrate include a plurality of display frames, in the first drive mode, the display frames include: a refresh frame and at least one maintain frame; the display substrate includes pixel circuits arranged in an array, the pixel circuits include a data signal line and a first initial signal line; the data signal line provides a first data signal in the maintain frame, the voltage value of the first data signal is constant, and/or the first initial signal line provides a first initial signal in the refresh frame and the maintain frame, the first initial signal is an AC signal.