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1.发明授权公开(公告)号：US10902810B2
公开(公告)日：2021-01-26
申请号：US15751066
申请日：2017-07-28
Applicant: BOE Technology Group Co., Ltd.
Inventor： Mingfu Han , Guangliang Shang , Xing Yao , Seung Woo Han , Jiha Kim , Haoliang Zheng , Lijun Yuan , Zhichong Wang
IPC: G09G3/36
Abstract: The present disclosure relates to an array substrate gate driving unit and an apparatus thereof, a driving method and a display apparatus. The array substrate gate driving unit includes: an input circuit, connected with an input signal terminal and a pull-up node PU; a pull-down circuit, connected with a first voltage signal terminal and the pull-up node PU; a pull-down control circuit, connected with the pull-down circuit via a pull-down node PD; an output circuit, connected with a clock signal terminal CLK, a second voltage signal terminal and a control circuit; a reset circuit, connected with a reset signal terminal Reset, the first voltage signal terminal and the pull-up node PU; and the control circuit, connected with the pull-up node PU and the output circuit.
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公开(公告)号：US10679565B2
公开(公告)日：2020-06-09
申请号：US16063448
申请日：2017-11-07
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jiha Kim , Seung Woo Han , Guangliang Shang , Haoliang Zheng , Xing Yao , Mingfu Han , Zhichong Wang , Lijun Yuan , Yun Sik Im , Yinglong Huang , Xue Dong
IPC: G09G3/3266 , G11C19/28 , H01L27/12 , G09G3/3208
Abstract: An array substrate, a display panel, a display device and a driving method. The array substrate includes: a plurality of first pixel units arranged in an array in a first region; a first gate driving circuit a second gate driving circuit; a plurality of first gate lines connected with the first gate driving circuit; and a plurality of second gate lines connected with the second gate driving circuit. A first portion of the plurality of first pixel units is connected with the plurality of first gate lines, and each first pixel unit in the first portion is connected with one of the plurality of first gate lines; and a second portion of the plurality of first pixel units is connected with the plurality of second gate lines, and each first pixel unit in the second portion is connected with one of the plurality of second gate lines.
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公开(公告)号：US20200258463A1
公开(公告)日：2020-08-13
申请号：US15768309
申请日：2017-10-31
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jiha Kim , Seungwoo Han , Guangliang Shang , Haoliang Zheng , Xing Yao , Zhichong Wang , Mingfu Han , Lijun Yuan , Yunsik IM , Jing Lv , Xue Dong
Abstract: A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.
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Patent Agency Ranking
公开(公告)号：US10504469B2
公开(公告)日：2019-12-10
申请号：US15768948
申请日：2017-10-17
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jiha Kim , Seung Woo Han , Guangliang Shang , Xing Yao , Haoliang Zheng , Mingfu Han , Zhichong Wang , Lijun Yuan , Yun Sik Im , Jing Lv , Yinglong Huang , Xue Dong
IPC: G09G3/36 , G11C19/28 , G09G3/3266 , G09G3/20 , G11C19/18
Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.
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公开(公告)号：US10475409B2
公开(公告)日：2019-11-12
申请号：US15796463
申请日：2017-10-27
Applicant: BOE Technology Group Co., Ltd.
Inventor： Mingfu Han , Xing Yao , Guangliang Shang , Haoliang Zheng , Seung-Woo Han , Jiha Kim , Lijun Yuan , Zhichong Wang
Abstract: The present disclosure discloses a gate drive circuit, a display panel and a driving method for the gate drive circuit. The gate drive circuit includes a plurality of shift register units connected in cascade; and further includes: buffer units which are in a one-to-one correspondence with shift register units at all levels, and touch control switch units which are in a one-to-one correspondence with shift register units at even levels. Each buffer unit in the gate drive circuit can increase the holding time of the effective pulse signal output by the shift register unit at a corresponding level by one line before resetting, and the effective pulse signal output by a buffer unit at an even level under the control of a touch control unit and the effective pulse signal output by a buffer unit at an adjacent previous odd level are reset at the same time.
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公开(公告)号：US10943552B2
公开(公告)日：2021-03-09
申请号：US15768309
申请日：2017-10-31
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jiha Kim , Seungwoo Han , Guangliang Shang , Haoliang Zheng , Xing Yao , Zhichong Wang , Mingfu Han , Lijun Yuan , Yunsik Im , Jing Lv , Xue Dong
IPC: G09G3/36 , G11C19/28 , G09G3/3266
Abstract: A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.
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7.发明申请公开(公告)号：US20200090611A1
公开(公告)日：2020-03-19
申请号：US15751066
申请日：2017-07-28
Applicant: BOE Technology Group Co., Ltd.
Inventor： Mingfu Han , Guangliang Shang , Xing Yao , Seung Woo Han , Jiha Kim , Haoliang Zheng , Lijun Yuan , Zhichong Wang
IPC: G09G3/36
Abstract: The present disclosure relates to an array substrate gate driving unit and an apparatus thereof, a driving method and a display apparatus. The array substrate gate driving unit includes: an input circuit, connected with an input signal terminal and a pull-up node PU; a pull-down circuit, connected with a first voltage signal terminal and the pull-up node PU; a pull-down control circuit, connected with the pull-down circuit via a pull-down node PD; an output circuit, connected with a clock signal terminal CLK, a second voltage signal terminal and a control circuit; a reset circuit, connected with a reset signal terminal Reset, the first voltage signal terminal and the pull-up node PU; and the control circuit, connected with the pull-up node PU and the output circuit.
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公开(公告)号：US10540938B2
公开(公告)日：2020-01-21
申请号：US15768948
申请日：2017-10-17
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jiha Kim , Seung Woo Han , Guangliang Shang , Xing Yao , Haoliang Zheng , Mingfu Han , Zhichong Wang , Lijun Yuan , Yun Sik Im , Jing Lv , Yinglong Huang , Xue Dong
IPC: G09G3/36 , G11C19/28 , G09G3/3266 , G09G3/20 , G11C19/18
Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.
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