-
公开(公告)号：US11868511B2
公开(公告)日：2024-01-09
申请号：US17794142
申请日：2021-08-05
Inventor： Xiangye Wei , Yiming Bai , Liming Xiu
Abstract: Provided is a digital fingerprint generator. The digital fingerprint generator includes: a control circuit, configured to generate a control word; a first pulse generation circuit, connected to the control circuit, and configured to output a first pulse signal in response to the control word; a second pulse generation circuit, connected to the control circuit, having a same structure as the first pulse generation circuit, and configured to output a second pulse signal in response to the control word; and an output circuit, connected to the first pulse generation circuit and the second pulse generation circuit, and configured to output a digital fingerprint based on the first pulse signal and the second pulse signal according to a predetermined first rule.
-
32.发明公开公开(公告)号：US20230409074A1
公开(公告)日：2023-12-21
申请号：US18459053
申请日：2023-08-31
Inventor： Xiangye Wei , Liming Xiu
IPC: G06F1/08
CPC classification number: G06F1/08
Abstract: A method for generating spread-spectrum synchronous clock signals includes comparing an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback; generating a first control signal and a second control signal; determining an integer part I of a control word F to track the first frequency; registering n levels for the first control signal and the second control signal to introduce n phase delays for randomly changing a fraction part r (0
-
公开(公告)号：US11799578B2
公开(公告)日：2023-10-24
申请号：US17413367
申请日：2020-01-19
Inventor： Xiangye Wei , Liming Xiu , Yiming Bai
CPC classification number: H04J3/0658 , H03L7/18 , H04J3/0641 , H04J3/0679
Abstract: This is provided a time synchronization method, including: an adjustment stage including N adjustment cycles, N being an integer greater than 1; in each adjustment cycle, generating a physical clock signal at least according to a pre-acquired frequency control word corresponding to the adjustment cycle, and obtaining logical time at least according to the physical clock signal and a physical time deviation; a clock slope of the physical clock signal generated in each adjustment cycle reaches its corresponding target value, and the target values of the clock slopes of the physical clock signals in the N adjustment cycles gradually approach 1; the physical time deviation is: a time difference between the reference time and the physical time corresponding to the physical clock signal in an Nth adjustment cycle at the end of the Nth adjustment cycle. A time synchronization device and a network node device are provided.
-
Patent Agency Ranking
34.发明授权公开(公告)号：US11689193B2
公开(公告)日：2023-06-27
申请号：US17765933
申请日：2021-03-09
Inventor： Xiangye Wei , Liming Xiu
Abstract: A clock signal generation circuit, a method for generating a clock signal, and an electronic device are provided, relating to the field of communications technology. In the clock signal generation circuit, an initial clock providing circuit can generate an initial clock signal having an initial frequency; a control word providing circuit can determine a target frequency offset of the initial frequency based on a detected target parameter and generate a frequency control word based on the target frequency offset; a target clock generating circuit can generate a target clock signal having a target output frequency based on the frequency control word and the initial clock signal, wherein the target output frequency is negatively correlated with a value of the frequency control word and positively correlated with the initial frequency.
-
35.发明申请公开(公告)号：US20230123009A1
公开(公告)日：2023-04-20
申请号：US16975258
申请日：2019-10-09
Inventor： Xiangye Wei , Liming Xiu
IPC: H03L7/089 , H03L7/099 , H03K19/173
Abstract: The present application discloses a circuit for generating spread-spectrum synchronous clock signal. The circuit includes a frequency detector comprising a fraction controller configured to compare an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback to generate a first control signal and a second control signal alternately for determining a control word to track the first frequency and a phase-shift controller configured to register n levels for the first control signal and the second control signal to introduce n phase delays for changing a fraction part of the control word randomly to provide a broadened boundary. The circuit also includes a digitally controlled oscillator configured to generate a synthesized periodic signal based on a base time unit, the first frequency, and the control word, with the second frequency being locked within the broadened boundary of the first frequency.
-
36.发明授权公开(公告)号：US11196454B2
公开(公告)日：2021-12-07
申请号：US16975261
申请日：2019-10-09
Inventor： Xiangye Wei , Liming Xiu , Yuhai Ma , Xin Li
Abstract: A digital transceiver is provided. The digital transceiver includes a clock generator configured to generate a first clock signal having a first frequency of a fixed value and a transmitter driven by the first clock signal of the first frequency to transmit data. Additionally, the digital transceiver includes an inverter coupled to the clock generator to generate an inverted first clock signal of the first frequency. Further, it includes a frequency detector configured to compare the first frequency with a second frequency of a feedback signal in a loop of feedback to determine a frequency control word F. Furthermore, it includes a digitally-controlled oscillator driven by the frequency control word F in the loop of feedback to output a second clock signal with a time-average frequency substantially synchronous to the first frequency with a boundary spread and a receiver driven by the second clock signal to receive the data.
-
公开(公告)号：US11031926B2
公开(公告)日：2021-06-08
申请号：US16975267
申请日：2019-10-21
Inventor： Xiangye Wei , Liming Xiu , Yiming Bai , Xin Li
Abstract: A digital clock circuit is provided. The digital clock circuit includes a first sub-circuit comprising a first digitally-controlled oscillator driven by a frequency control word to control a first output frequency synthesized from multiple first pulses, and a first frequency divider to generate a trigger signal having a frequency equal to 1/M of the first output frequency. The digital clock circuit also includes a second sub-circuit comprising a loop of feedback including a frequency detector to compare an input frequency with a feedback frequency, a controller to adjust the frequency control word, a second digitally-controlled oscillator driven by the frequency control word plus a constant to control a second output frequency synthesized from multiple second pulses induced by the trigger signal, and a second frequency divider to set the feedback frequency equal to 1/N of the second output frequency in the loop of feedback.
-
公开(公告)号：US20190052276A1
公开(公告)日：2019-02-14
申请号：US15952531
申请日：2018-04-13
Applicant: BOE Technology Group Co., Ltd.
Inventor： Liming Xiu
CPC classification number: H03L7/085 , H03K5/135 , H03L7/099 , H03L7/0996
Abstract: A frequency compensator, an electronic device, and a frequency compensation method are disclosed. The frequency compensator includes a control circuit and a frequency compensation circuit. The control circuit is configured to generate a frequency control word according to an initial frequency and an target frequency. The frequency compensation circuit is configured to receive an input signal of an initial frequency, and to generate and output an output signal of a compensated frequency according to the frequency control word and the input signal of the initial frequency.
-
-
-
-
-
-
-
Search Results
38
records
(took 0.027 seconds)
