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公开(公告)号：US20190235294A1
公开(公告)日：2019-08-01
申请号：US16180419
申请日：2018-11-05
Inventor： Zhengkui WANG , Jian SUN , Fei HUANG , Jiguo WANG , Yun QIAO , Xiaozhou ZHAN , Han ZHANG , Zhen WANG , Wenwen QIN , Lele CONG , Peng LIU , Jianjun ZHANG
IPC: G02F1/1333 , G02F1/1362 , G02F1/1368 , G06F3/044 , G06F3/041
Abstract: An array substrate includes a base substrate, a plurality of first signal lines extending in a first direction, a plurality of second signal lines located on a different layer from the first signal lines and extending in a second direction intersecting the first direction, and a plurality of touch signal lines extending in the second direction disposed on the base substrate. Each touch signal line includes a first touch line segment and a second touch line segment, the first touch line segment disposed on the same layer as the first signal lines, and at least partially overlapping with at least one of the second signal lines in a direction perpendicular to a surface of the base substrate, the second touch line segment disposed on a different layer from the first signal lines, and the first touch line segment electrically connected with the second touch line segment through a first via.
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32.发明申请Array Substrate and Manufacturing Method Thereof, Display Panel and Display Device 有权阵列基板及其制造方法，显示面板和显示设备公开(公告)号：US20160327842A1
公开(公告)日：2016-11-10
申请号：US14906350
申请日：2015-07-16
Inventor： Yun QIAO , Jian SUN , Cheng LI , Seongjun AN
IPC: G02F1/1362 , H01L27/12 , H01L27/02 , G09G3/36
CPC classification number: G02F1/136204 , G02F1/1362 , G02F1/136209 , G02F1/13624 , G02F1/136286 , G09G3/3648 , G09G3/3659 , G09G2300/043 , G09G2330/023 , H01L27/0255 , H01L27/124 , H01L27/127 , H01L29/78633
Abstract: The invention provides an array substrate and a manufacturing method thereof, a display panel and a display device, the array substrate includes a base substrate, and a data line, a switching device and a voltage compensation module arranged on the base substrate, the switching device is connected between the data line and the voltage compensation module so that the data line is electrically connected to the voltage compensation module when a voltage on the data line is lower than a preset low voltage or higher than a preset high voltage. The array substrate uses a PN junction as the switching device between the data line and the voltage compensation module, and due to a low leakage current between a P terminal and an N terminal of the PN junction, the power consumption of the array substrate can be reduced.
Abstract translation: 本发明提供一种阵列基板及其制造方法，显示面板及显示装置，所述阵列基板包括基板，配置在所述基板上的数据线，开关元件及电压补偿模块，所述开关元件 连接在数据线和电压补偿模块之间，使得当数据线上的电压低于预设的低电压或高于预设的高电压时，数据线电连接到电压补偿模块。 阵列基板使用PN结作为数据线和电压补偿模块之间的开关器件，并且由于P端子和PN结的N端之间的低漏电流，阵列基板的功耗可以是 减少
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公开(公告)号：US20160283009A1
公开(公告)日：2016-09-29
申请号：US14368642
申请日：2013-12-03
Inventor： Jian SUN , Xueguang HAO , Xuelu WANG , Cheng LI
IPC: G06F3/041 , G09G3/36 , G02F1/1368 , G02F1/1335 , G02F1/1343 , G02F1/1362 , G06F3/044 , G02F1/1333
CPC classification number: G06F3/0416 , G02F1/13338 , G02F1/133512 , G02F1/134309 , G02F1/13439 , G02F1/136286 , G02F1/1368 , G02F2201/40 , G06F3/0412 , G06F3/044 , G06F2203/04103 , G06F2203/04111 , G09G3/3677 , G09G3/3688 , G09G3/3696 , G09G2300/0809 , G09G2300/0842 , G09G2310/0202 , G09G2310/0278
Abstract: The disclosure discloses an in-cell touch panel and a display device, wherein a touch sensing structural layer for implementing a touch control function is added between an upper substrate and a lower substrate, the touch sensing structural layer includes first touch sensing electrodes and second touch sensing electrodes both provided in a same layer, insulated from each other and arranged crosswise, wherein an orthographic projection on the lower substrate, of a graph of the added touch sensing structural layer is located in a region where a graph of the black matrix layer is located, capable of avoiding occupying an aperture rate of pixel units.
Abstract translation: 本公开公开了一种单元内触摸面板和显示装置，其中，用于实现触摸控制功能的触摸感测结构层被添加在上基板和下基板之间，触摸感测结构层包括第一触摸感测电极和第二触摸 两个设置在同一层中的感测电极彼此绝缘并且交叉排列，其中所述添加的触摸感测结构层的曲线图的下基板上的正投影位于黑矩阵层的图形的区域中 位于，能够避免占据像素单位的开口率。
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公开(公告)号：US20240266367A1
公开(公告)日：2024-08-08
申请号：US18021197
申请日：2022-05-27
IPC: H01L27/12
CPC classification number: H01L27/1251 , H01L27/1225 , H01L27/127
Abstract: An array substrate includes a display area and a peripheral area on a side of the display area, and includes a base substrate, at least one low temperature polycrystalline silicon thin film transistor on the base substrate and in the peripheral area, and at least one oxide thin film transistor on the base substrate and in the display area; the low temperature polycrystalline silicon thin film transistor includes a low temperature polycrystalline silicon semiconductor layer, a first gate, and a first source and a first drain, which are sequentially arranged along a direction away from the base substrate; the oxide thin film transistor includes an oxide semiconductor layer, a second gate, and a second source and a second drain, which are sequentially arranged along the direction away from the base substrate; and the first source and the first drain are each in a different layer from the second gate.
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公开(公告)号：US20240258335A1
公开(公告)日：2024-08-01
申请号：US18630971
申请日：2024-04-09
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jiguo WANG , Jian SUN , Zhao ZHANG , Liang TIAN , Weida QIN , Zhen WANG , Han ZHANG , Wenwen QIN , Xiaoyan YANG , Yue SHAN , Wei YAN , Jian ZHANG , Deshuai WANG , Yadong ZHANG , Jiantao LIU
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L27/124 , G02F1/136209 , G02F1/136213 , G02F1/136222 , G02F1/13629 , G02F1/1368 , H01L27/1255
Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; and a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); where the pattern unit (171a) further includes a second bump (1712) located within a central area surrounded by each of the first bumps (1710), and the spacing groove (1711) on a same side of the first bump (1710) and the second bump (1712) is arranged in a non-straight shape.
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Patent Agency Ranking
公开(公告)号：US20240212772A1
公开(公告)日：2024-06-27
申请号：US17794991
申请日：2021-09-28
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wei YAN , Zhen WANG , Wenwen QIN , Han ZHANG , Deshuai WANG , Jian ZHANG , Yue SHAN , Xiaoyan YANG , Yadong ZHANG , Jian SUN
CPC classification number: G11C19/28 , G09G3/20 , G09G2310/0286
Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.
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公开(公告)号：US20230041917A1
公开(公告)日：2023-02-09
申请号：US17797983
申请日：2021-09-08
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jiguo WANG , Jian SUN , Jiantao LIU , Xiaoyan YANG
IPC: G02F1/1343 , G02F1/1362 , G02F1/1368 , G02F1/1335 , G02F1/1339 , H01L27/12
Abstract: An array substrate includes: a first substrate; a plurality of gate lines and a plurality of data lines; a plurality of thin film transistors; and a plurality of reflective electrodes. The plurality of gate lines and the plurality of data lines define a plurality of sub-pixel regions. A thin film transistor is located in a sub-pixel region. A reflective electrode is located in the sub-pixel region and electrically connected to the thin film transistor in the same sub-pixel region. Each reflective electrode has a border including a plurality of first sub-borders extending in a first direction, a plurality of second sub-borders extending in a second direction, and a plurality of chamfer borders each connecting a first sub-border and a second sub-border that are adjacent; and an intersection of extension lines of the first sub-border and the second sub-border is located outside the border of the reflective electrode.
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公开(公告)号：US20220367530A1
公开(公告)日：2022-11-17
申请号：US17765304
申请日：2021-04-13
Inventor： Yongbo JU , Pengfei CUI , Jian SUN , Deshuai WANG , Xiangkai SHEN , Jianbin GAO , Jiannan WANG , Guangshuai WANG
IPC: H01L27/12 , H01L23/00 , G02F1/1345 , G02F1/1333 , G06F3/041 , G06F3/044
Abstract: An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.
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公开(公告)号：US20220327987A1
公开(公告)日：2022-10-13
申请号：US17763719
申请日：2021-05-21
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
IPC: G09G3/20
Abstract: A display substrate, a display panel, a display apparatus, and a display driving method are provided. The display substrate includes: a display region and a peripheral region at a periphery thereof. Gate lines, data lines and a pixel array are in the display region. The pixel array includes pixel units each coupled to a corresponding gate line and data line, and color mixing pixel columns each including multiple pixel units emitting light of different colors and including periodic structures along the column direction. The number of pixel units in each periodic structure is constant. A gate driving circuit is in the peripheral region and includes cascaded shift registers each having a cascading signal output terminal and scanning signal output terminals each coupled to a corresponding gate line. The number of scanning signal output terminals of each shift register is equal to the number of pixel units in each periodic structure.
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公开(公告)号：US20210360818A1
公开(公告)日：2021-11-18
申请号：US16491340
申请日：2019-03-29
Inventor： Yu LEI , Jian SUN , Haoran JING , Wenhong TIAN , Zhen TANG , Ziqiang GUO , Xinjian LIU , Ruifeng QIN , Lili CHEN , Hao ZHANG , Feng PAN
Abstract: A VR integrated machine and a running method thereof are provided. The VR integrated machine includes a heat generating device, a heat conducting member and thermoelectric conversion member, the heat conducting member is connected with the heat generating device, the thermoelectric conversion member has a first end connected with the heat conducting member, and is configured to generate electrical energy and to supply the electrical energy to the UR integrated machine.
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