公开(公告)号：US20220344282A1

公开(公告)日：2022-10-27

申请号：US17730527

申请日：2022-04-27

Applicant: Applied Materials, Inc.

Inventor： Pradeep K. Subrahmanyan ,  Sean S. Kang ,  Sony Varghese

IPC: H01L23/00 ,  G03F7/20 ,  H01L21/66

Abstract: Provided are methods of reducing the stress of a semiconductor wafer. A wafer map of a free-standing wafer is created using metrology tools. The wafer map is then converted into a power spectral density (PSD) using a spatial frequency scale. The fundamental component of bow is then compensated with a uniform film, e.g., silicon nitride (SiN), deposited on the back side of the wafer.

公开(公告)号：US20210351188A1

公开(公告)日：2021-11-11

申请号：US16868851

申请日：2020-05-07

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese

IPC: H01L27/108 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/265

Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One non-limiting method may include providing a device, the device including a plurality of angled structures formed from a substrate, a bitline and a dielectric between each of the plurality of angled structures, and a drain disposed along each of the plurality of angled structures. The method may further include providing a plurality of mask structures of a patterned masking layer over the plurality of angled structures, the plurality of mask structures being oriented perpendicular to the plurality of angled structures. The method may further include etching the device at a non-zero angle to form a plurality of pillar structures.

公开(公告)号：US20210265357A1

公开(公告)日：2021-08-26

申请号：US17238572

申请日：2021-04-23

Applicant: APPLIED Materials, Inc.

Inventor： Sony Varghese ,  Min Gyu Sung

IPC: H01L27/108 ,  H01L21/768 ,  H01L29/417 ,  H01L21/311

Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One method may include forming a plurality of trenches and angled structures, each angled structure including a first sidewall opposite a second sidewall, wherein the second sidewall extends over an adjacent trench. The method may include forming a spacer along a bottom surface of the trench, along the second sidewall, and along the first sidewall, wherein the spacer has an opening at a bottom portion of the first sidewall. The method may include forming a drain in each of the angled structures by performing an ion implant, which impacts the first sidewall through the opening at the bottom portion of the first sidewall. The method may include removing the spacer from the first sidewall, forming a bitline over the spacer along the bottom surface of each of the trenches, and forming a series of wordlines along the angled structures.

公开(公告)号：US11037788B2

公开(公告)日：2021-06-15

申请号：US16687529

申请日：2019-11-18

Applicant: Applied Materials, Inc.

Inventor： Min Gyu Sung ,  Sony Varghese

IPC: H01L29/06 ,  H01L21/033

Abstract: The present disclosure relates to a method for creating regions of different device types. The substrate is divided into a first device region and a second device region. A target etch layer is formed on a substrate. A bottom mandrel layer is formed on the target etch layer. A plurality of first pillars of a top mandrel material is formed on the bottom mandrel layer in the first device region, having a first pitch. A plurality of first spacers is formed along sidewalls of each of the plurality of first pillars. An optical planarization layer (OPL) is formed over the plurality of first pillars, the plurality of first spacers, and a top surface of the bottom mandrel layer in the first device region. A plurality of second pillars of the top mandrel material is formed on the bottom mandrel layer in the second device region, having a second pitch.

公开(公告)号：US20210125994A1

公开(公告)日：2021-04-29

申请号：US16664107

申请日：2019-10-25

Applicant: APPLIED Materials, Inc.

Inventor： Sony Varghese ,  Min Gyu Sung

IPC: H01L27/108

Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One method may include forming a plurality of trenches and angled structures, each angled structure including a first sidewall opposite a second sidewall, wherein the second sidewall extends over an adjacent trench. The method may include forming a spacer along a bottom surface of the trench, along the second sidewall, and along the first sidewall, wherein the spacer has an opening at a bottom portion of the first sidewall. The method may include forming a drain in each of the angled structures by performing an ion implant, which impacts the first sidewall through the opening at the bottom portion of the first sidewall. The method may include removing the spacer from the first sidewall, forming a bitline over the spacer along the bottom surface of each of the trenches, and forming a series of wordlines along the angled structures.

公开(公告)号：US10903211B1

公开(公告)日：2021-01-26

申请号：US16542658

申请日：2019-08-16

Applicant: APPLIED Materials, Inc.

Inventor： Anthony Renau ,  Min Gyu Sung ,  Sony Varghese ,  Morgan Evans ,  Naushad K. Variam ,  Tassie Andersen

IPC: H01L27/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure is directed to structures and processing for three-dimensional transistor devices. In some approaches, a method may include providing a plurality of fin structures formed from a substrate, the plurality of fin structures disposed subjacent to a hard mask layer, and directing angled ions at the plurality of fin structures. The angled ions may form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, wherein the angled ions etch the plurality of fin structures to form a stack of isolated nanowires within the plurality of fin structures. The method may further include removing the hard mask layer, and forming a stopping layer over the stack of isolated nanowires.

公开(公告)号：US10686033B2

公开(公告)日：2020-06-16

申请号：US16186027

申请日：2018-11-09

Applicant: APPLIED Materials, Inc.

Inventor： Min Gyu Sung ,  Jae Young Lee ,  Johannes Van Meer ,  Sony Varghese ,  Naushad K. Variam

IPC: H01L29/06 ,  H01L21/76 ,  H01L29/417 ,  H01L21/762 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, and forming a second STI material over a second fin section of the plurality of fins, wherein the second fin section is left remaining following removal of the first fin section. The method may further include recessing the STI material and the second STI material, forming a spin-on-carbon (SOC) layer over the semiconductor device, and implanting the STI material and the second STI material through the SOC layer.

公开(公告)号：US20200152519A1

公开(公告)日：2020-05-14

申请号：US16186004

申请日：2018-11-09

Applicant: APPLIED Materials, Inc.

Inventor： Min Gyu Sung ,  Jae Young Lee ,  Johannes Van Meer ,  Sony Varghese ,  Naushad K. Variam

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L21/768

Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include recessing the STI material to reveal an upper portion of the plurality of fins, implanting the semiconductor device, and forming a capping layer over the plurality of fins and the STI material. The method may further include removing a first fin section of the plurality of fins and a first portion of the capping layer, wherein a second fin section of the plurality of fins remains following removal of the first fin section.

公开(公告)号：US10580651B2

公开(公告)日：2020-03-03

申请号：US16003902

申请日：2018-06-08

Applicant: Applied Materials, Inc.

Inventor： Min Gyu Sung ,  Sony Varghese

IPC: H01L29/06 ,  H01L21/033

Abstract: The present disclosure relates to a method for creating regions of different device types on a substrate having different pitches. The method includes dividing a substrate into a first device type region and a second device type region. The method further includes forming a target etch layer on the substrate. The method further includes forming a bottom mandrel layer on the target etch layer. The method further includes forming a plurality of alternating first pillars of a top mandrel material and first trenches between the first pillars on the bottom mandrel layer in the first device type region. The plurality of first pillars has a first pitch. The method further includes forming a plurality of alternating second pillars of the top mandrel material and second trenches between the second pillars on the bottom mandrel layer in the second device type region. The plurality of second pillars has a second pitch. The method further includes depositing tone inversion material in the first trenches.