公开(公告)号：US06973524B1

公开(公告)日：2005-12-06

申请号：US09736883

申请日：2000-12-14

Applicant: Richard L. Solomon ,  Timothy E. Hoglund

Inventor： Richard L. Solomon ,  Timothy E. Hoglund

IPC: G06F13/14 ,  G06F13/40

CPC classification number: G06F13/4031

Abstract: The present invention is directed to an interface. An interface system suitable for coupling a first bus interface controller with a second bus interface controller includes a first bus interface controller and a second bus interface controller in which the second bus interface controller is coupled to the first bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data.

Abstract translation: 本发明涉及一种接口。 适于将第一总线接口控制器与第二总线接口控制器耦合的接口系统包括第一总线接口控制器和第二总线接口控制器，其中第二总线接口控制器经由接口耦合到第一总线接口控制器。 该接口包括适合于对事务进行排队的命令排队接口，适用于报告事务完成的命令完成界面和适于传送数据的数据传输接口。

公开(公告)号：US06925519B2

公开(公告)日：2005-08-02

申请号：US10202774

申请日：2002-07-25

Applicant: Brian A. Day ,  Timothy E. Hoglund ,  Ganesan Viswanathan ,  Ayyavu Vetrivel

Inventor： Brian A. Day ,  Timothy E. Hoglund ,  Ganesan Viswanathan ,  Ayyavu Vetrivel

IPC: G06F3/06 ,  G06F13/00 ,  G06F13/36 ,  G06F13/40

CPC classification number: G06F13/4027 ,  G06F3/0607 ,  G06F3/0661 ,  G06F3/0689

Abstract: A device generally comprising a first circuit and a second circuit. The first circuit may be configured to (i) communicate with a host via a first bus (ii) using a small computer system interface (SCSI) protocol having a plurality of command descriptor blocks. The second circuit configured to (i) communicate with a remote device with a via a second bus, (ii) using an advanced technology attachment (ATA) protocol and (iii) translate a subset of the command descriptor blocks to the ATA protocol in application specific hardware.

Abstract translation: 一种通常包括第一电路和第二电路的装置。 第一电路可以被配置为（i）使用具有多个命令描述符块的小型计算机系统接口（SCSI）协议经由第一总线（ii）与主机通信。 第二电路被配置为（i）经由第二总线与远程设备通信，（ii）使用高级技术附件（ATA）协议和（iii）在应用中将命令描述符块的子集转换到ATA协议 具体硬件。

公开(公告)号：US06185620B2

公开(公告)日：2001-02-06

申请号：US09054849

申请日：1998-04-03

Applicant: David M. Weber ,  Timothy E. Hoglund ,  Stephen M. Johnson ,  John M. Adams ,  Mark A. Reber

Inventor： David M. Weber ,  Timothy E. Hoglund ,  Stephen M. Johnson ,  John M. Adams ,  Mark A. Reber

IPC: G06F1100

CPC classification number: H04L49/901 ,  H04L29/06 ,  H04L49/90 ,  H04L49/9031 ,  H04L69/12

Abstract: A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on ship processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order. Additionally, the context managers also determine when all frames within a sequence have been received. A link control unit is provided in which loop management is provided when the host is connected to a loop. Management of the loop includes implementing mechanisms to initiate acquisition of the loop and initiate a release of the loop in response to conditions in which data is received and transmitted by the host and by other nodes on the loop.

Abstract translation: 一种用于通过将主机连接到节点的结构将数据从主机传送到节点的方法和装置。 提供了一种芯片架构，其中协议引擎提供用于传送数据的船舶处理，使得来自芯片中的各种组件的频繁中断可以被处理而无需主机处理器的干预。 另外，提供上下文管理器来发送和接收数据。 协议引擎创建传输活动的列表，该列表由上下文管理器遍历，后者又以独立于协议引擎的方式执行列出的活动。 在接收数据时，上下文管理器提供一种机制来处理来自各种源的数据帧，而不需要来自协议引擎的干预。 当接收到数据时，上下文管理器能够处理来自不同来源的帧，这些帧到达无序。 另外，上下文管理器还确定序列中的所有帧何时已被接收。 提供了一种链路控制单元，其中当主机连接到环路时，提供循环管理。 循环的管理包括执行机制以启动循环的获取并且响应于由主机和循环中的其他节点接收和发送数据的条件来启动循环的释放。

公开(公告)号：US09286136B1

公开(公告)日：2016-03-15

申请号：US13476474

申请日：2012-05-21

Applicant: Horia C. Simionescu ,  Timothy E. Hoglund ,  Robert L. Sheffield

Inventor： Horia C. Simionescu ,  Timothy E. Hoglund ,  Robert L. Sheffield

IPC: G06F3/00 ,  G06F9/52 ,  G06F9/30

CPC classification number: G06F9/526 ,  G06F9/3004 ,  G06F17/30362

Abstract: A region lock (RL) method and system for ensuring data integrity is disclosed. The method and system in accordance with the present disclosure works in conjunction with a balanced-tree based RL scheme. By eliminating steps and checks that in most cases are unnecessary, the relatively high overhead associated with the balanced-tree based RL scheme may be reduced. For instance, the solution in accordance with the present disclosure may utilize a hash table to determine whether RL overlap checks may be bypassed for certain I/O commands. Since the new solution requires very little processing, therefore by reducing unnecessary RL overlap checks, RL overhead may be dramatically reduced and may lead to significant increases in overall system performance.

Abstract translation: 公开了一种用于确保数据完整性的区域锁（RL）方法和系统。 根据本公开的方法和系统结合基于平衡树的RL方案来工作。 通过消除在大多数情况下是不必要的步骤和检查，可以减少与基于平衡树的RL方案相关联的相对高的开销。 例如，根据本公开的解决方案可以利用散列表来确定对于某些I / O命令可以绕过RL重叠检查。 由于新解决方案需要很少的处理，因此通过减少不必要的RL重叠检查，RL开销可能会大大降低，并可能导致整体系统性能的显着提高。

公开(公告)号：US09043642B2

公开(公告)日：2015-05-26

申请号：US13083394

申请日：2011-04-08

Applicant: Peter B. Chon ,  James Yu ,  David M. Olson ,  Timothy E. Hoglund ,  Gary J. Piccirillo

Inventor： Peter B. Chon ,  James Yu ,  David M. Olson ,  Timothy E. Hoglund ,  Gary J. Piccirillo

IPC: G06F11/00 ,  G06F11/14 ,  G06F1/30 ,  G06F11/10

CPC classification number: G06F11/1441 ,  G06F1/30 ,  G06F11/1052

Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.

Abstract translation: 公开了电力隔离和备用系统。 当检测到电源故障条件时，临时存储器被刷新到SDRAM。 在刷新之后，接口被停止，除了SDRAM子系统之外的大多数芯片的电源被去除。 SDRAM子系统将数据从SDRAM复制到闪存。 在路上，数据可以被加密，和/或计算数据完整性签名。 为了恢复数据，SDRAM子系统将数据从闪存复制到SDRAM。 一路上，正在恢复的数据可能被解密，和/或检查数据完整性签名。

公开(公告)号：US08332849B2

公开(公告)日：2012-12-11

申请号：US12454626

申请日：2009-05-20

Applicant: Richard L. Solomon ,  Timothy E. Hoglund

Inventor： Richard L. Solomon ,  Timothy E. Hoglund

IPC: G06F9/455 ,  G06F3/00

CPC classification number: G06F9/546 ,  G06F9/5061 ,  G06F2209/548

Abstract: The present invention is directed to an information handling system device for operatively coupling with a device implementing Input/Output (I/O) virtualization for data transmission. The information handling system device may be configured for executing an operating system control program to manage one or more guest operating systems on the information handling system device. The operating system control program may include a paravirtualization driver for formulating a work queue entry according to the I/O virtualization of the device. Data may be transmitted between the one or more guest operating systems and the device via the paravirtualization driver.

Abstract translation: 本发明涉及一种用于与实现用于数据传输的输入/输出（I / O）虚拟化的设备可操作地耦合的信息处理系统设备。 信息处理系统设备可以被配置为执行操作系统控制程序来管理信息处理系统设备上的一个或多个客户操作系统。 操作系统控制程序可以包括用于根据设备的I / O虚拟化来制定工作队列条目的半虚拟化驱动器。 可以经由半虚拟化驱动器在一个或多个客户操作系统和设备之间传送数据。

公开(公告)号：US20100306420A1

公开(公告)日：2010-12-02

申请号：US12765027

申请日：2010-04-22

Applicant: Stephen B. Johnson ,  Timothy E. Hoglund

Inventor： Stephen B. Johnson ,  Timothy E. Hoglund

IPC: G06F13/28

CPC classification number: G06F13/28 ,  Y02D10/14

Abstract: A hardware automated IO path, comprising a message transport unit for transporting an IO request to a local memory via a DMA operation and determining a LMID for associating with a request descriptor of the IO request; a fastpath engine for validating the request descriptor and creating a fastpath descriptor based on the request descriptor; a data access module for performing an IO operation based on the fastpath descriptor and posting a completion message into the fastpath completion queue upon a successful completion of the IO operation. The fastpath engine is further configured for: receiving the completion message, releasing the IO request stored in the local memory, and providing a reply message based on the completion message. The message transport unit is further configured for providing the reply message in response to the IO request.

Abstract translation: 一种硬件自动IO路径，包括用于经由DMA操作将IO请求传送到本地存储器并确定用于与所述IO请求的请求描述符相关联的LMID的消息传输单元; 用于验证请求描述符并基于请求描述符创建快速路径描述符的快速引擎; 数据访问模块，用于在成功完成IO操作时，基于快速路径描述符执行IO操作并将完成消息发布到快速路径完成队列中。 快速引擎还被配置为：接收完成消息，释放存储在本地存储器中的IO请求，以及基于完成消息提供回复消息。 消息传送单元还被配置为响应于IO请求来提供应答消息。

公开(公告)号：US06732198B1

公开(公告)日：2004-05-04

申请号：US09910658

申请日：2001-07-20

Applicant: Stephen B. Johnson ,  Timothy E. Hoglund ,  Daniel E. Ballare

Inventor： Stephen B. Johnson ,  Timothy E. Hoglund ,  Daniel E. Ballare

IPC: G06F1314

CPC classification number: G06F9/30043 ,  G06F9/30032 ,  G06F9/3861 ,  G06F9/3879

Abstract: A circuit and associated methods of operation for a standardized scatter/gather list processor component within DMACs and intelligent IOPs. The standardized circuit architecture and methods provide a register interface and associated processing capabilities to simplify firmware processing to save and restore context information regarding block transfer operations that are paused and resumed prior to completion. Furthermore, the invention provides for architecture and associated methods for processing of standard scatter/gather list elements by a standardized scatter/gather list processor embedded within DMACs and IOPs. Specifically, as applied in the context of SCSI or Fiber Channel IOPs, the scatter/gather list processor of the present invention simplifies IOP firmware processing to save the current block transfer context on occurrence of a SCSI disconnect and to restore the saved context on occurrence of a SCSI reselect.

Abstract translation: DMAC和智能IOP中的标准散射/收集列表处理器组件的电路和相关操作方法。 标准化电路架构和方法提供了寄存器接口和相关联的处理能力，以简化固件处理以保存和恢复关于在完成之前暂停和恢复的块传送操作的上下文信息。 此外，本发明提供了通过嵌入DMAC和IOP内的标准化分散/收集列表处理器来处理标准分散/收集列表元素的架构和相关方法。 具体地说，如在SCSI或光纤通道IOP的上下文中应用的，本发明的分散/收集列表处理器简化了IOP固件处理，以便在出现SCSI断开时保存当前块传输上下文，并且在出现 SCSI重新选择。

公开(公告)号：US06647483B1

公开(公告)日：2003-11-11

申请号：US09872883

申请日：2001-06-01

Applicant: Timothy E. Hoglund ,  William M. Ortega ,  Roger T. Clegg

Inventor： Timothy E. Hoglund ,  William M. Ortega ,  Roger T. Clegg

IPC: G06F1202

CPC classification number: G06F12/0284

Abstract: A circuit comprising a processor and a translation circuit. The processor may be configured to present a first address. The translation circuit may be configured to (i) determine a mask and an offset, (ii) mask the first address to produce a first masked address, (iii) mask a second address to produce a second masked address, (iv) compare the first masked address with the second masked address, and (v) add the offset to the first address to present a third address in response to the first masked address being at least as great as the second masked address.

Abstract translation: 一种包括处理器和转换电路的电路。 处理器可以被配置为呈现第一地址。 翻译电路可以被配置为（i）确定掩码和偏移，（ii）掩蔽第一地址以产生第一掩蔽地址，（iii）掩蔽第二地址以产生第二掩蔽地址，（iv）将 具有第二屏蔽地址的第一掩蔽地址，以及（v）响应于第一掩蔽地址至少与第二掩蔽地址一样大，将偏移添加到第一地址以呈现第三地址。

公开(公告)号：US06321342B1

公开(公告)日：2001-11-20

申请号：US09274566

申请日：1999-03-23

Applicant: Brian A. Day ,  Timothy E. Hoglund

Inventor： Brian A. Day ,  Timothy E. Hoglund

IPC: G06F110

CPC classification number: G06F1/08

Abstract: A method of interfacing a third circuit with a first circuit that operates based upon a first clock signal and a second circuit that operates based upon a second clock signal includes the step of applying the first clock signal and the second clock signal to a clock selector for the third circuit. The method further includes the step of transferring first data signals between the third circuit and the first circuit at a first rate based upon the first clock signal. Another step of the method includes causing the clock selector to apply the first clock signal to the third circuit prior to the step of transferring the first data signals between the third circuit and the first circuit. Yet another step of the method includes transferring second data signals between the third circuit and the second circuit at a second rate based upon the second clock signal. Furthermore, the method includes causing the clock selector to apply the second clock signal to the third circuit prior to the step of transferring the second data signals between the third circuit and the second circuit. Various apparatus for implementing the method are also disclosed.

Abstract translation: 将第三电路与基于第一时钟信号操作的第一电路和基于第二时钟信号操作的第二电路接口的方法包括将第一时钟信号和第二时钟信号施加到时钟选择器的步骤 第三回路。 该方法还包括基于第一时钟信号以第一速率在第三电路和第一电路之间传送第一数据信号的步骤。 该方法的另一步骤包括使得时钟选择器在第三电路和第一电路之间传送第一数据信号的步骤之前将第一时钟信号施加到第三电路。 该方法的另一步骤包括基于第二时钟信号以第二速率在第三电路和第二电路之间传送第二数据信号。 此外，该方法包括使得时钟选择器在第三电路和第二电路之间传送第二数据信号的步骤之前将第二时钟信号施加到第三电路。 还公开了用于实现该方法的各种装置。