公开(公告)号：US06723618B2

公开(公告)日：2004-04-20

申请号：US10206602

申请日：2002-07-26

申请人： Russell Meyer ,  Jeffrey W. Honeycutt ,  Stephen R. Porter

发明人： Russell Meyer ,  Jeffrey W. Honeycutt ,  Stephen R. Porter

IPC分类号： H01L218238

CPC分类号： H01L21/76205

摘要： Field isolation structures and methods of forming field isolation structures are described. In one implementation, the method includes etching a trench within a monocrystalline silicon substrate. The trench has sidewalls and a base, with the base comprising monocrystalline silicon. A dielectric material is formed on the sidewalls of the trench. Epitaxial monocrystalline silicon is grown from the base of the trench and over at least a portion of the dielectric material. An insulating layer is formed over the epitaxial monocrystalline silicon. According to one implementation, the invention includes a field isolation structure formed within a monocrystalline silicon comprising substrate. The field isolation structure includes a trench having sidewalls. A dielectric material is received on the sidewalls within the trench. Monocrystalline silicon is received within the trench between the dielectric material of the sidewalls. An insulating layer is received over the monocrystalline silicon within the trench. Additional implementations are contemplated.

摘要翻译： 描述了现场隔离结构和形成场隔离结构的方法。 在一个实施方案中，该方法包括蚀刻单晶硅衬底内的沟槽。 沟槽具有侧壁和基底，底部包括单晶硅。 介电材料形成在沟槽的侧壁上。 外延单晶硅从沟槽的底部至少部分介电材料生长。 在外延单晶硅上形成绝缘层。 根据一个实施方案，本发明包括在包含单晶硅的衬底内形成的场隔离结构。 场隔离结构包括具有侧壁的沟槽。 电介质材料被容纳在沟槽内的侧壁上。 单晶硅被接纳在侧壁的电介质材料之间的沟槽内。 绝缘层被接纳在沟槽内的单晶硅上。 考虑附加实现。

公开(公告)号：US06515925B2

公开(公告)日：2003-02-04

申请号：US09805933

申请日：2001-03-15

申请人： Scot M. Graham ,  Scott J. Derner ,  Stephen R. Porter

发明人： Scot M. Graham ,  Scott J. Derner ,  Stephen R. Porter

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.

公开(公告)号：US06385098B2

公开(公告)日：2002-05-07

申请号：US09836947

申请日：2001-04-17

申请人： Hal W. Butler ,  Stephen L. Casper ,  Stephen R. Porter

发明人： Hal W. Butler ,  Stephen L. Casper ,  Stephen R. Porter

IPC分类号： G11C1604

CPC分类号： G11C11/4074

摘要： An internal voltage regulator for a synchronous random access memory (“SDRAM”) uses a regulator circuit to supply power to charge pumps that is separate from a regulator circuit that supplies power to the arrays of the SDRAM. The regulator supplies an output voltage to the charge pumps that is maintained constant as the external supply voltage is increased beyond its normal operating range. In contrast, a regulated circuit that supplies power to the arrays increases as the supply voltage is increase beyond its normal operating range. As a result, the voltage regulator allows the arrays to be stress tested with a relatively high regulated output voltage without applying an excessive and potentially damaging regulated output voltage to the charge pumps.

摘要翻译： 用于同步随机存取存储器（“SDRAM”）的内部电压调节器使用调节器电路来为与将SDRAM供电的稳压器电路分离的电荷泵供电。 调节器为电荷泵提供输出电压，当外部电源电压提高到正常工作范围以上时，电荷泵保持恒定。 相比之下，向阵列供电的稳压电路随着电源电压增加超过正常工作范围而增加。 因此，电压调节器允许阵列以相对较高的调节输出电压进行压力测试，而不会对电荷泵施加过多的，潜在的破坏性的稳压输出电压。

公开(公告)号：US6114878A

公开(公告)日：2000-09-05

申请号：US023639

申请日：1998-02-13

申请人： Daniel R. Loughmiller ,  Stephen R. Porter

发明人： Daniel R. Loughmiller ,  Stephen R. Porter

IPC分类号： H03K19/173 ,  H03K19/00

CPC分类号： H03K19/1732 ,  H03K19/1731 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171

摘要： A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including a CMOS multiplexer controlled by a fuse or anti-fuse, an NMOS or PMOS pass gate controlled by a fuse or anti-fuse, or even a fusible link which is severed to effect isolation. Additionally, a circuit is provided that switchably isolates one of two contact pads from a logic circuit.

摘要翻译： 一旦不再需要接触垫，就提供一个电路来隔离接触垫与芯片的逻辑电路。 该电路可以采用许多形式，包括由熔丝或反熔丝控制的CMOS多路复用器，由保险丝或反熔丝控制的NMOS或PMOS通孔，或甚至被切断以实现隔离的可熔链路。 此外，提供了一种电路，其可切换地将两个接触焊盘之一与逻辑电路隔离。

公开(公告)号：US5369317A

公开(公告)日：1994-11-29

申请号：US989252

申请日：1992-12-11

申请人： Stephen L. Casper ,  Stephen R. Porter

发明人： Stephen L. Casper ,  Stephen R. Porter

IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C11/419 ,  H03K19/003 ,  H03K17/08

CPC分类号： H03K19/00315 ,  G11C11/419 ,  G11C5/147 ,  G11C7/12 ,  H03K19/00384

摘要： The invention is a circuit and method for controlling a high potential at a significant node by controlling the potential at a control input to an electrical device in electrical communication with the significant node. The potential of the control input is controlled by a control circuit. In a first embodiment the control circuit is a potential generator, and in a second embodiment the control circuit is a programmable circuit. The programmable circuit provides a potential at the control input that is directly proportional to a supply potential until a maximum potential is reached at which time the control input is maintained at the maximum potential.

摘要翻译： 本发明是一种用于通过控制与重要节点电通信的电气设备的控制输入处的电位来控制重要节点处的高电位的电路和方法。 控制输入​​的电位由控制电路控制。 在第一实施例中，控制电路是电位发生器，在第二实施例中，控制电路是可编程电路。 可编程电路在控制输入端提供与供电电位成正比的电位，直到达到最大电位，此时控制输入保持在最大电位。

公开(公告)号：US5304506A

公开(公告)日：1994-04-19

申请号：US29088

申请日：1993-03-10

申请人： Stephen R. Porter ,  Navjot Chhabra

发明人： Stephen R. Porter ,  Navjot Chhabra

IPC分类号： H01L21/02 ,  H01L21/70

CPC分类号： H01L28/40

摘要： The present invention discloses an on chip decoupling capacitor structure having a first decoupling capacitor with one electrode formed in the conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. The second electrode is a common electrode to a second decoupling capacitor overlying and thereby coupled in parallel to said first decoupling capacitor. The second capacitor's first electrode is the common electrode and its second electrode is made of conductively doped polysilicon. The electrodes made of the conductively doped polysilicon may be further enhanced by forming a silicided material, such as tungsten silicide, thereon. The decoupling capacitors' dielectric can be formed from high dielectric constant materials, such as TEOS, oxide, nitride or any combination thereof. The second decoupling capacitor could be fabricated over field oxide and used as a single capacitor having a first and second conductively doped polysilicon electrodes (either silicided or non-silicided) with a capacitor dielectric sandwiched in between.

摘要翻译： 本发明公开了一种片上去耦电容器结构，其具有在导电掺杂硅衬底中形成的一个电极的第一去耦电容器和由导电掺杂多晶硅制成的第二电极。 第二电极是与第一去耦电容器并联并由此并联到第一去耦电容器的第二去耦电容器的公共电极。 第二电容器的第一电极是公共电极，其第二电极由导电掺杂的多晶硅制成。 由导电掺杂多晶硅制成的电极可以通过在其上形成诸如硅化钨的硅化物材料进一步增强。 去耦电容器的电介质可以由高介电常数材料形成，例如TEOS，氧化物，氮化物或其任何组合。 第二去耦电容器可以在场氧化物上制造，并且用作具有第一和第二导电掺杂多晶硅电极（硅化或非硅化）的单个电容器，其间夹有电容器电介质。

公开(公告)号：US5297087A

公开(公告)日：1994-03-22

申请号：US54902

申请日：1993-04-29

申请人： Stephen R. Porter

发明人： Stephen R. Porter

IPC分类号： G11C8/12 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C8/12 ,  G11C11/401

摘要： A semiconductor memory device includes a plurality of row lines, a plurality of column lines, and a common storage cell plate. The memory device also includes a cell plate generator which produces a reference voltage. The reference voltage is connected to the common storage cell plate. A row decoder connects a row line voltage to selected individual row lines. A stress mode detection circuit receives a row line stress voltage and generates a stress mode signal in response. The row decoder is responsive to the stress mode signal to simultaneously bias all of the row lines to the row line stress voltage. At least one equilibrate circuit is also connected to receive the stress mode signal and is responsive to the stress mode signal to bias the column lines to the reference voltage. The memory device is furthermore responsive to the stress mode signal to ground the reference voltage. The circuits described create a voltage stress differential between the column lines, the row lines, and the common storage cell plate. This voltage stress differential is greater than any voltage differential occurring between the row lines, the column lines, and the storage cell plate during normal memory access operations. The voltage stress differential is maintained for a relatively long period to induce failure of marginally defective dielectric layers within the semiconductor memory device.

摘要翻译： 半导体存储器件包括多条行线，多条列线和公共存储单元板。 存储器件还包括产生参考电压的单元板发生器。 参考电压连接到公共存储单元板。 行解码器将行线电压连接到所选择的各行行。 应力模式检测电路接收行线应力电压并产生应力模式信号。 行解码器响应于应力模式信号，以将所有行线同时偏置到行线应力电压。 还连接至少一个平衡电路以接收应力模式信号，并且响应于应力模式信号以将列线偏置到参考电压。 存储器件还响应于应力模式信号将参考电压接地。 所描述的电路在列线，行线和公共存储单元板之间产生电压应力差。 该电压应力差异大于正常存储器访问操作期间在行线，列线和存储单元板之间发生的任何电压差。 电压应力差异保持相对长的时间段以引起半导体存储器件内的边缘损坏的电介质层的失效。

公开(公告)号：US07746720B2

公开(公告)日：2010-06-29

申请号：US11879396

申请日：2007-07-17

申请人： Scott J. Derner ,  Venkatraghavan Bringivijayaraghavan ,  Abhay S. Dixit ,  Scot M. Graham ,  Stephen R. Porter ,  Ethan A. Williford

发明人： Scott J. Derner ,  Venkatraghavan Bringivijayaraghavan ,  Abhay S. Dixit ,  Scot M. Graham ,  Stephen R. Porter ,  Ethan A. Williford

IPC分类号： G11C8/00

CPC分类号： G11C11/412 ,  G11C11/4085

摘要： Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.

摘要翻译： 利用负字线架构降低存储器件漏极漏极泄漏（GIDL）的技术。 更具体地，提供了一种方法和装置，用于确定存储器阵列的一部分中的任何字线是否是活动的。 如果多个字线中的任一个是活动的，则该部分中的每个非活动字线被耦合到负电压电平。 如果多个字线中没有一个是有效的，则多个字线中的每个字线被耦合到地来减少GIDL。

公开(公告)号：US07336522B2

公开(公告)日：2008-02-26

申请号：US11489119

申请日：2006-07-19

申请人： Scott J. Derner ,  Stephen R. Porter ,  Scot M. Graham ,  Ethan A. Williford ,  Kevin G. Duesman

发明人： Scott J. Derner ,  Stephen R. Porter ,  Scot M. Graham ,  Ethan A. Williford ,  Kevin G. Duesman

IPC分类号： G11C11/24

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/1048 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/002

摘要： A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.

摘要翻译： 提供了一种减少存储器件中的电流的方法和装置。 外围设备控制信号被转换为字线关断电压电平，例如负字线电压。 转换后的信号可防止外围设备在字线关闭模式下传导电流，即使发生字线数字短路。 控制信号可以包括列选择装置的列选择信号和用于感测放大器的有源上拉信号等。 此外，为存储器件提供具有高电阻和低电阻分量的均衡电路。 均衡电路限制电流，即使发生字线数字短路。

公开(公告)号：US07173855B2

公开(公告)日：2007-02-06

申请号：US10930526

申请日：2004-08-31

申请人： Stephen R. Porter ,  Scott J. Derner

发明人： Stephen R. Porter ,  Scott J. Derner

IPC分类号： G11C11/34

CPC分类号： H01L23/5252 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.

摘要翻译： 公开了通过轻度掺杂电连接区域来调节反熔丝编程电流的方法和装置，使得区域的电阻以非线性方式响应于电压变化。 以这种方式，可以产生可变电阻器或可变电阻晶体管，其响应于施加的电压而改变其电阻，并且因此可限制编程电流，而不限制对串行连接的反熔丝的较小的读取电流。