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    3D INTEGRATED CIRCUIT STACK-WIDE SYNCHRONIZATION CIRCUIT
    31.
    发明申请
    3D INTEGRATED CIRCUIT STACK-WIDE SYNCHRONIZATION CIRCUIT 有权

    公开(公告)号：US20130049825A1

    公开(公告)日：2013-02-28

    申请号：US13217767

    申请日：2011-08-25

    申请人： Joel A. Silberman ,  Matthew R. Wordeman

    发明人： Joel A. Silberman ,  Matthew R. Wordeman

    IPC分类号： H03L7/00

    CPC分类号： H03L7/00 ,  G06F1/12 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

    PROGRAMMING THE BEHAVIOR OF INDIVIDUAL CHIPS OR STRATA IN A 3D STACK OF INTEGRATED CIRCUITS
    32.
    发明申请
    PROGRAMMING THE BEHAVIOR OF INDIVIDUAL CHIPS OR STRATA IN A 3D STACK OF INTEGRATED CIRCUITS 有权
    编写集成电路三维堆栈中个体或行为的行为

    公开(公告)号：US20130049796A1

    公开(公告)日：2013-02-28

    申请号：US13607020

    申请日：2012-09-07

    申请人： LIANG-TECK PANG ,  JOEL A. SILBERMAN ,  MATTHEW R. WORDEMAN

    发明人： LIANG-TECK PANG ,  JOEL A. SILBERMAN ,  MATTHEW R. WORDEMAN

    IPC分类号： H03K19/00

    CPC分类号： G01R31/318558 ,  G01R31/318513 ,  G01R31/318572 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.

    摘要翻译： 在具有两个或多个层的3D芯片堆栈中提供了层次管理器。 层管理器包括多个可扫描配置寄存器，每个配置寄存器布置在两个或更多个层中的相应一个上，用于存储一组位。 该组比特被配置为对存储有该组比特的两个或更多个层中的对应的一个或其上的装置的操作进行编程。 此外，还提供了3D堆栈内的3D堆栈和堆栈扫描电路内的层标识符。

    THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS
    35.
    发明申请
    THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS 有权
    用于控制集成电路中静态功耗的三端子开关

    公开(公告)号：US20090321710A1

    公开(公告)日：2009-12-31

    申请号：US12551643

    申请日：2009-09-01

    申请人： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    发明人： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    IPC分类号： H01L45/00

    CPC分类号： H01L45/1226 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148

    摘要： A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

    摘要翻译： 开关电路包括连接在电压供给端子和逻辑子块之间的多个三端子PCM开关装置。 每个开关装置包括设置在第一端子和第二端子之间接触的PCM，加热装置，其设置成接触在第二端子和第三端子之间，加热装置位于PCM附近，并且被配置为切换 PCM的可变形部分在较低电阻状态和较高电阻状态之间; 以及绝缘层，其被配置为将加热器与所述PCM材料电隔离，并且所述加热器与所述第一端子电隔离。 第一个PCM开关器件的第三个端子耦合到一个设置/复位开关，其余的PCM开关器件的第三个端子以级联配置耦合到相邻PCM开关器件的第二个端子。

    HERMETIC SEAL AND RELIABLE BONDING STRUCTURES FOR 3D APPLICATIONS
    36.
    发明申请
    HERMETIC SEAL AND RELIABLE BONDING STRUCTURES FOR 3D APPLICATIONS 有权
    用于3D应用的HERMETIC SEAL和可靠的结合结构

    公开(公告)号：US20090140404A1

    公开(公告)日：2009-06-04

    申请号：US12038501

    申请日：2008-02-27

    申请人： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

    发明人： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

    IPC分类号： H01L23/10

    CPC分类号： H01L25/50 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

    摘要翻译： 一种密封的微电子结构，其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。 每个芯片沿着其周边包括连续的接合材料，以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。 每个支撑柱向外延伸，使得当至少两个芯片彼此定位时，支撑柱彼此配合。 至少两个芯片之间的密封由芯片彼此的重叠关系产生，使得接合材料和支撑柱彼此配合。 因此，当至少两个芯片配合在一起时形成密封，并且导致粘合芯片结构。

    Differential and Hierarchical Sensing for Memory Circuits
    37.
    发明申请
    Differential and Hierarchical Sensing for Memory Circuits 有权
    用于存储器电路的差分和分层检测

    公开(公告)号：US20080175085A1

    公开(公告)日：2008-07-24

    申请号：US12057011

    申请日：2008-03-27

    申请人： John Edward Barth ,  Paul C. Parries ,  William Robert Reohr ,  Matthew R. Wordeman

    发明人： John Edward Barth ,  Paul C. Parries ,  William Robert Reohr ,  Matthew R. Wordeman

    IPC分类号： G11C7/06

    CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/4094

    摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.

    摘要翻译： 存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。 每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。 至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。

    Differential and hierarchical sensing for memory circuits
    39.
    发明授权
    Differential and hierarchical sensing for memory circuits 有权
    存储电路的差分和分层感测

    公开(公告)号：US07382672B2

    公开(公告)日：2008-06-03

    申请号：US11754422

    申请日：2007-05-29

    申请人： John Edward Barth, Jr. ,  Paul C. Parries ,  William Robert Reohr ,  Matthew R. Wordeman

    发明人： John Edward Barth, Jr. ,  Paul C. Parries ,  William Robert Reohr ,  Matthew R. Wordeman

    IPC分类号： G11C7/02

    CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/4094

    摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.

    摘要翻译： 存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。 每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。 至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。

    Charge pump system having multiple independently activated charge pumps and corresponding method
    40.
    发明授权
    Charge pump system having multiple independently activated charge pumps and corresponding method 有权
    具有多个独立激活的电荷泵的电荷泵系统及相应的方法

    公开(公告)号：US06275096B1

    公开(公告)日：2001-08-14

    申请号：US09460820

    申请日：1999-12-14

    申请人： Louis L. C. Hsu ,  Oliver Weinfurtner ,  Matthew R. Wordeman

    发明人： Louis L. C. Hsu ,  Oliver Weinfurtner ,  Matthew R. Wordeman

    IPC分类号： G05F302

    CPC分类号： H02M3/07

    摘要： A charge pump generator system and method is provided which more precisely maintains the level of an internally generated voltage supply by operating some or all of the available charge pumps depending upon the voltage level reached by the voltage supply. When the voltage supply is far from its target level, a first group and a second group of charge pumps are operated. The first group may preferably have a faster pumping rate or a greater number of charge pumps than the second group. When the voltage supply exceeds a first predetermined level, the first group of charge pumps is switched off while the second group remains on, such that the rate of charge transfer slows. The second group continues operating until a second, e.g. target, voltage level is exceeded. The slower rate of charge transfer then effective reduces overshoot, ringing and noise coupled onto the voltage supply line. Preferably, at least one charge pump operates in both standby and active modes, thereby reducing chip area.

    摘要翻译： 提供一种电荷泵发电机系统和方法，其通过根据电压源达到的电压水平操作一些或全部可用电荷泵，从而更精确地保持内部产生的电压源的电平。 当电源远离其目标电平时，第一组和第二组电荷泵被操作。 第一组可优选具有比第二组更快的泵送速率或更大数量的电荷泵。 当电压提供超过第一预定电平时，第一组电荷泵关闭，而第二组保持接通，使得电荷转移速率变慢。 第二组继续运行直到第二组，例如， 目标，超过电压电平。 然后，较慢的电荷转移速率有效地减少了耦合到电源线上的过冲，振铃和噪声。 优选地，至少一个电荷泵在备用和有源模式下工作，从而减少芯片面积。