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44 条记录 (耗时 0.023 秒)

    Data processor processing a jump instruction
    32.
    发明授权
    Data processor processing a jump instruction 失效
    数据处理器处理跳转指令

    公开(公告)号：US5592637A

    公开(公告)日：1997-01-07

    申请号：US537000

    申请日：1995-09-29

    申请人： Masahito Matsuo

    发明人： Masahito Matsuo

    IPC分类号： G06F9/32 ,  G06F9/38

    CPC分类号： G06F9/3804 ,  G06F9/322 ,  G06F9/3842

    摘要： A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.

    摘要翻译： 一种数据处理器，包括：指令提取单元111，其从存储指令的存储器中取出指令; 指令解码112，其对从指令获取单元111取出的指令进行解码; 指令执行单元，其基于指令解码单元112的解码结果执行指令; 程序计数器（DPC）29，其保持在指令解码单元112中解码的指令的地址; 和连接到指令提取单元111和程序计数器（DPC）29的分支目标地址计算单元1相加从指令提取单元111传送的分支位移字段的值和从程序计数器传送的指令地址 （DPC）29，并将相加结果传送到指令提取单元111，使得可以通过流水线处理有效地处理跳转指令。

    Pipeline processor, with return address stack storing only pre-return processed address for judging validity and correction of unprocessed address
    34.
    发明授权
    Pipeline processor, with return address stack storing only pre-return processed address for judging validity and correction of unprocessed address 失效
    管道处理器，返回地址堆栈仅存储用于判断有效性的预返回处理地址和未处理地址的校正

    公开(公告)号：US5193205A

    公开(公告)日：1993-03-09

    申请号：US317253

    申请日：1989-02-28

    申请人： Masahito Matsuo ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toyohiko Yoshida

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/40

    CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/321 ,  G06F9/3842 ,  G06F9/3867

    摘要： A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

    摘要翻译： 根据本发明的数据处理器使得可以在流水线处理的初始阶段对子程序返回指令执行关于返回地址的预分支处理，因此通过提供专用的堆栈存储器（PC堆栈） 到用于仅存储子程序返回指令的返回地址的程序计数器（PC），在执行流水线处理机构的执行阶段中的子程序调用指令时，将子程序的返回地址推送到PC堆栈， 在指令解码阶段对子例程返回指令进行解码时，对从PC堆栈弹出的地址进行分支处理。

    Multiple sequentially transferrable stackpointers in a data processor in a pipelining system
    35.
    发明授权
    Multiple sequentially transferrable stackpointers in a data processor in a pipelining system 失效
    在流水线系统中的数据处理器中的多个可顺序传输的堆栈指针

    公开(公告)号：US4974158A

    公开(公告)日：1990-11-27

    申请号：US506498

    申请日：1990-04-09

    申请人： Yukari Watanabe ,  Toyohiko Yoshida ,  Masahito Matsuo ,  Yuichi Saito ,  Toru Shimizu

    发明人： Yukari Watanabe ,  Toyohiko Yoshida ,  Masahito Matsuo ,  Yuichi Saito ,  Toru Shimizu

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3824 ,  G06F9/3863 ,  G06F9/3867

    摘要： This invention relates to a data processor with pipelining system, which is provided with at least two stages having working stackpointer respectively, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and each working stackpointer corresponding to each stage is renewed synchronizing with pipelining processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to corresponding working stackpointers synchronizing with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

    摘要翻译： 本发明涉及一种具有流水线系统的数据处理器，其具有分别具有工作堆栈指针的至少两个级，并且构造成使得每个级可以独立地指代对应于每个级的工作堆栈指针，并且每个工作堆栈指针对应于每个级 与流水线处理同步地更新，使得当在堆栈推送寻址模式和堆栈弹出寻址模式下执行包括指定操作数的多个指令时，在地址计算阶段执行的地址计算的结果被顺序地传送到相应的工作堆栈指针同步 通过管道传送指令，从而可以使数据处理器顺利地执行流水线处理。

    Instruction fetching in data processing apparatus
    36.
    发明授权
    Instruction fetching in data processing apparatus 失效
    数据处理装置中的指令取出

    公开(公告)号：US4796175A

    公开(公告)日：1989-01-03

    申请号：US34093

    申请日：1987-04-02

    申请人： Masahito Matsuo ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toyohiko Yoshida

    IPC分类号： G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/381

    摘要： A microprocessor has a main memory, an instruction execution unit, and instruction queue for prefetching a series of instructions from the main memory, and an instruction cache. The instruction cache prefetches and stores an instruction next to those stored in the instruction queue by use of its address tag as an index when an amount of data fetched in the instruction queue is below a constant value. The fetching of the next instruction into the instruction queue from the instruction cache is achieved at the time to execute the same instruction again.

    摘要翻译： 微处理器具有主存储器，指令执行单元和用于从主存储器预取一系列指令的指令队列和指令高速缓存。 当指令队列中读取的数据量低于常数值时，指令高速缓存将存储在指令队列中的指令与存储在指令队列中的指令相对应地存储并存储指令。 在执行相同的指令时，实现从指令高速缓存取出下一条指令到指令队列中。

    Data processor capable of executing two instructions having operand interference at high speed in parallel
    37.
    发明授权
    Data processor capable of executing two instructions having operand interference at high speed in parallel 失效
    能够并行地以高速执行具有操作数干扰的两个指令的数据处理器

    公开(公告)号：US06178492B1

    公开(公告)日：2001-01-23

    申请号：US08555425

    申请日：1995-11-09

    申请人： Masahito Matsuo

    发明人： Masahito Matsuo

    IPC分类号： G06F938

    CPC分类号： G06F9/3822 ,  G06F9/3853

    摘要： A data processor comprises an instruction decoding unit having two decoders decoding respective instructions of an instruction group consisting of a plurality of instructions including a first instruction and a second instruction succeeding the first instruction, and a judging unit judging whether or not a combination of the first instruction and the second instruction can be executed in parallel and a bus for transferring two data in parallel between an operand access unit and an integer operation unit. The data processor uses a superscalar technique. Two instructions having an operand interference can be executed in parallel at high speed and two instructions accessing a memory can be executed in parallel without considerable hardware.

    摘要翻译： 数据处理器包括：指令解码单元，具有两个解码器，对由包括第一指令和第一指令之后的第二指令的多个指令组成的指令组的相应指令进行解码，以及判断单元，判断第一 指令和第二指令可并行执行，总线用于在操作数存取单元和整数运算单元之间并行传送两个数据。 数据处理器使用超标量技术。 可以高速并行地执行具有操作数干扰的两个指令，并且可以并行地执行访问存储器的两个指令，而没有相当大的硬件。

    Data processing system capable of executing groups of instructions, including at least one arithmetic instruction, in parallel
    38.
    发明授权
    Data processing system capable of executing groups of instructions, including at least one arithmetic instruction, in parallel 失效
    数据处理系统能够并行地执行包括至少一个算术指令的指令组

    公开(公告)号：US6131158A

    公开(公告)日：2000-10-10

    申请号：US759499

    申请日：1996-12-04

    申请人： Masahito Matsuo ,  Toru Shimizu ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toru Shimizu ,  Toyohiko Yoshida

    IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/38 ,  G06F11/28 ,  G06F11/36

    CPC分类号： G06F9/3865 ,  G06F11/28 ,  G06F11/3648 ,  G06F9/3001 ,  G06F9/30149 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3869 ,  G06F9/3875

    摘要： A data processor performs various types of EIT (exception, interrupt, trap) processing in connection with the execution of the preceding and following instructions in parallel. In one embodiment, an exception is detected resulting from processing the previous instruction in the pair being executed in parallel before completion of instruction processing where the exception requires re-execution. When the exception is detected a control means prevents the execution means from executing both preceding and following instructions. An additional feature is a control unit that controls when an interrupt is accepted during parallel execution. In another embodiment, a first decoder outputs suppressing information when the preceding instruction is a predetermined instruction having a possibility of causing a trap. A validity judgment circuit prevents the second decoded result from being issued when suppressing information is generated.

    摘要翻译： 数据处理器并行执行与执行前述和后续指令相关的各种类型的EIT（异常，中断，陷阱）处理。 在一个实施例中，检测到异常，这是由于在执行异常需要重新执行的指令处理完成之前处理在该对中的先前指令并行执行的异常。 当检测到异常时，控制装置防止执行装置执行前述和后续指令。 一个附加功能是控制单元，用于控制在并行执行期间接受中断的时间。 在另一个实施例中，当前一条指令是具有引起陷阱的可能性的预定指令时，第一解码器输出抑制信息。 当产生抑制信息时，有效性判断电路防止发出第二解码结果。

    Circular buffer with two different step sizes
    39.
    发明授权
    Circular buffer with two different step sizes 失效
    具有两个不同步长的圆形缓冲器

    公开(公告)号：US5924114A

    公开(公告)日：1999-07-13

    申请号：US890618

    申请日：1997-07-09

    申请人： Toshiyuki Maruyama ,  Masahito Matsuo

    发明人： Toshiyuki Maruyama ,  Masahito Matsuo

    IPC分类号： G06F12/02 ,  G06F9/355 ,  G06F9/38 ,  G06F12/00

    CPC分类号： G06F9/3552 ,  G06F9/3824 ,  G06F9/3885

    摘要： A control unit (112) makes different judgments on the end address, depending on whether 1-word access or 2-word access, based on a post-update signal (507) and a 2-word access signal (508) which are internally generated and a coincidence signal (511) on the high-order 14 bits and another coincidence signal (512) on the bit 14 which are outputted from a comparator (158), and outputs a judgment result to a selector (155) as a selection signal (510). The selector (155) selects one of an output from an ALU (153) and an output from a latch (159) (the MOD.sub.-- S register 156) based on the selection signal (510). Having this structure, a data processor which enables access with modulo addressing in two different data-units can be provided.

    摘要翻译： 根据内部的更新后信号（507）和2字访问信号（508），控制单元（112）根据1字访问或2字访问对结束地址做出不同的判断 从比较器（158）输出的高位14比特上的比特14上的重合信号（511）和比特14上的另一符合信号（512），并将判断结果输出到选择器（155）作为选择 信号（510）。 选择器（155）基于选择信号（510）从ALU（153）的输出和来自锁存器（159）（MOD-S寄存器156）的输出中选择一个。 具有这种结构，可以提供能够以两种不同的数据单元进行模寻址的数据处理器。

    Data processor and method of processing data
    40.
    发明授权
    Data processor and method of processing data 失效
    数据处理器和数据处理方法

    公开(公告)号：US5901301A

    公开(公告)日：1999-05-04

    申请号：US699944

    申请日：1996-08-20

    申请人： Masahito Matsuo ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toyohiko Yoshida

    IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/32 ,  G06F9/34 ,  G06F9/355 ,  G06F9/38

    CPC分类号： G06F9/3893 ,  G06F9/30014 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30178 ,  G06F9/322 ,  G06F9/325 ,  G06F9/3552 ,  G06F9/3822 ,  G06F9/3853 ,  G06F9/3889

    摘要： A second decoder (114) of an instruction decode unit (119) decodes an operation code for a multiply-add operation, and a second operation unit (117) receives two data stored in a register file (115) to perform the multiply-add operation. In parallel with the operations of the second decoder (114) and the second operation unit (117), a first decoder (113) of the instruction decode unit (119) decodes an operation code for 2 data load, and an operand access unit (104) causes two data (e.g., n bits each) stored in an internal data memory (105) to be transferred in parallel in the form of combined 2n-bit data to a first operation unit (116). Then, two predetermined registers of the register file (115) store the respective n-bit data from the first operation unit (116).

    摘要翻译： 指令解码单元（119）的第二解码器（114）解码用于乘法运算的操作码，并且第二操作单元（117）接收存储在寄存器文件（115）中的两个数据，以执行乘法运算 操作。 与第二解码器（114）和第二操作单元（117）的操作并行，指令解码单元（119）的第一解码器（113）对用于2个数据负载的操作码和操作数存取单元（ 104）使得存储在内部数据存储器（105）中的两个数据（例如，每个n位）以并入的2n位数据的形式并行传送到第一操作单元（116）。 然后，寄存器文件（115）的两个预定寄存器存储来自第一操作单元（116）的相应的n位数据。